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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1982

Allowable silicon wafer thickness versus diameter for ingot rotation ID wafering

Inner diameter (ID) wafering of ingot rotation reduce the ID saw blade diameter was investigated. The blade thickness can be reduced, resulting in minimal kerf loss. However, significant breakage of wafers occurs during the rotation wafering as the wafer thickness decreases. Fracture mechanics was used to develop an equation relating wafer thickness, diameter and fracture behavior at the point of fracture by using a model of a wafer, supported by a center column and subjected to a cantilever force. It is indicated that the minimum allowable wafer thickness does not increase appreciably with increasing wafer diameter and that fracture through the thickness rather than through the center supporting column limits the minimum allowable wafer thickness. It is suggested that the minimum allowable wafer thickness can be reduced by using a vacuum chuck on the wafer surface to enhance cleavage fracture of the center core and by using 111 ingots.

Chen, C. P.↗
NASA NTRS1984

Minimum wafer thickness by rotated ingot ID wafering

The efficient utilization of materials is critical to certain device applications such as silicon for photovoltaics or diodes and gallium-gadolinium-garnet for memories. A variety of slicing techniques has been investigated to minimize wafer thickness and wafer kerf. This paper presents the results of analyses of ID wafering of rotated ingots based on predicted fracture behavior of the wafer as a result of forces during wafering and the properties of the device material. The analytical model indicated that the minimum wafer thickness is controlled by the depth of surface damage and the applied cantilever force. Both of these factors should be minimized. For silicon, a minimum thickness was found to be approximately 200 x 10 - 6th m for conventional sizes of rotated ingot wafering. Fractures through the thickness of the wafer rather than through the center supporting column were found to limit the minimum wafer thickness. The model suggested that the use of a vacuum chuck on the wafer surface to enhance cleavage fracture of the center supporting core and, with silicon, by using 111-line-type ingots could have potential for reducing minimum wafer thickness.

Chen, C. P.↗
DOE OSTI2021

Wafer-based charged particle accelerator, wafer components, methods, and applications

A wafer-based charged particle accelerator includes a charged particle source and at least one RF charged particle accelerator wafer sub-assembly and a power supply coupled to the at least one RF charged particle accelerator wafer sub-assembly. The wafer-based charged particle accelerator may further include a beam current-sensor. The wafer-based charged particle accelerator may further include at least a second RF charged particle accelerator wafer sub-assembly and at least one ESQ charged particle focusing wafer. Fabrication methods are disclosed for RF charged particle accelerator wafer sub-assemblies, ESQ charged particle focusing wafers, and the wafer-based charged particle accelerator.

Lal, Amit↗
NASA NTRS1982

Minimum silicon wafer thickness for ID wafering

An analytical model, based on fracture mechanics analysis, is proposed for estimating the minimum wafer thickness as a function of the diameter requirement for solar cells. The conditions under which the model can be applied are discussed with reference to the critical flaw size, the applied force, and the width of the side support. It is shown that the equivalent cantilever force applied during ID slicing can be estimated from the wafering mechanical yield data. The width of the wafer side support was found to be a significant factor in controlling the minimum allowable wafer thickness during slicing. Wafer side support width requirements were found to increase with decreasing wafer thickness.

Chen, C. P.↗
NASA NTRS1982

Wafering economies for industrialization from a wafer manufacturer's viewpoint

The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

Rosenfield, T. P.↗
NASA NTRS2013

Silicon Alignment Pins: An Easy Way to Realize a Wafer-to-Wafer Alignment

Submillimeter heterodyne instruments play a critical role in addressing fundamental questions regarding the evolution of galaxies as well as being a crucial tool in planetary science. To make these instruments compatible with small platforms, especially for the study of the outer planets, or to enable the development of multi-pixel arrays, it is essential to reduce the mass, power, and volume of the existing single-pixel heterodyne receivers. Silicon micromachining technology is naturally suited for making these submillimeter and terahertz components, where precision and accuracy are essential. Waveguide and channel cavities are etched in a silicon bulk material using deep reactive ion etching (DRIE) techniques. Power amplifiers, multiplier and mixer chips are then integrated and the silicon pieces are stacked together to form a supercompact receiver front end. By using silicon micromachined packages for these components, instrument mass can be reduced and higher levels of integration can be achieved. A method is needed to assemble accurately these silicon pieces together, and a technique was developed here using etched pockets and silicon pins to align two wafers together.

Jung-Kubiak, Cecile↗
NASA NTRS2016

Silicon Alignment Pins: An Easy Way to Realize a Wafer-To-Wafer Alignment

A silicon alignment pin is used to align successive layers of components made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.

Jung-Kubiak, Cecile↗
NASA NTRS2018

Wafer-To-Wafer Alignment Method

A silicon alignment pin is used to align successive layer of component made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.

Jung-Kubiak, Cecile↗
DOE OSTI2020

Low Cost (CAPEX and variable): Tool design for cell and module fabrication with thin, free-standing silicon wafers

This project aimed to develop technologies that can potentially enable free-standing thin (<80 μm) wafer in today’s manufacturing lines with high production yield, and thereby reduce capex barriers of silicon photovoltaics cells and modules. One of the major benefits is that thin wafer dramatically reduces the amount of polysilicon required. As a result, it can lead to reduction in the capital expenditures associated with polysilicon refining and wafer fabrication, which together are more than half of the total capital expenditure to manufacture Si PV module. We focused our efforts on developing the tools needed to enable high yield fabrication of wafer, cell, and module with thin silicon wafers. However, as the wafer thickness reduces, the major challenge is that wafer breakage increases significantly. Three technological areas were explored in this project to improve the production yield of the silicon wafer, namely detection of edge cracks via dark-field near-infrared (NIR) scattering; (2) wafer handling using controlled temperature profiles; (3) manufacturable low-stress cell interconnection for multiwire. First, the formation of wafer cracks in submillimeter length is one of the reasons that causes wafer breakages. Crack detection tools are needed to enable us to locate and track the wafer crack during manufacturing, so that we can improve the process to reduce initialization. The state-of-the-art crack detection technique cannot fulfill the need for measuring submillimeter edge cracks detrimental for thin wafers. The prototype developed in this project demonstrates the scanning of microcracks near wafer edges. With a semi-automatic laboratory setup, the submillimeter cracks were reliably detected near the edges in multi-Si wafers. The smallest detectable crack is 200 µm in length in slow scans; and submillimeter cracks are detected in high-throughput scans at the scan speed of >0.5 m/s, which is compatible with the inline detection of a manufacturing line at least 1 sec/wafer. This detection limit is a significant advancement in comparison to the benchmarked industrial tool. Second, wafer handling with the well-controlled temperature profile was thought to be the solution to reduce crack initiation and propagation during the manufacturing. However, without crack detection being widely adopted in production line, we did not find a strong industrial pull toward this technology. We did an initial literature survey and then diverted our efforts to the other tasks. Third, the innovation on low-stress multi-wire interconnection tackles a fundamental problem in the standard interconnection scheme. The standard over-under “zig-zag” interconnection induces a significant amount of stress into the soldering point on the cell whenever PV module is under stress, e.g., thermal cycling, transportation, and installation. Therefore, the interconnection process was re-designed in this project to allow for significant movement between adjacent solar cells, e.g., due to thermal expansion, without building up stresses on the solar cells or solder joints. The new interconnection method with the cross-connect wire also simplifies the tabbing and stringing process by replacing the standard over-under method with an off-cell interconnect from top to bottom. A manual tabbing and stringing tool for this new process was prototyped in the lab to demonstrate the fabrication of this new interconnection design. During the test with brass sheets as our “testing cells”, it was found that the mechanical cycling test only broke the interconnection after more than 50,000 cycles, which is equivalent to more than 130 years of the day-and-night thermal cycles. Lastly, throughout the project, we continuously analyzed the PV market with techno-economic analysis to identify the opportunity for thin Si adoption. Even though the drastic cost reduction has already happened in the past five years, our analysis results indicated that we can still save quite significantly in both manufacturing cost and factory capex, Particularly, in order to grow the PV manufacturing capacity to multi-terawatt level, reducing the thickness of silicon wafer is one of the most effective ways to quickly reduce factory capex, and sustain the high growth rate. The technologies developed in this project are readily available to provide some assistances in tackling the production yield problem.

14 SOLAR ENERGY↗
DOE OSTI2024

Passivated Contacts for Direct Wafer Product (Final Technical Report)

This TCF project developed a thin-oxide (SiO 2 )/polycrystalline silicon (poly-Si) passivated contact solar cell on CubicPV's (formally 1366 Technologies, Inc.) Direct Wafer® Product (DWP) kerfless wafers. The project used two NREL-developed technologies described in U.S. Patent No. 9,911,873, Hydrogenation of Passivated Contacts and U.S. Patent Application Serial No. 15/890,172, Doped Passivated Contacts . The project was motivated by a potential higher efficiency cell (compared to a PERC cell) using passivated contacts on the ultra-low cost kerfless wafers grown using the Direct Wafer process. The hope was to accelerate market adoption of the cell and wafer by delivering the lowest LCOE in the PV industry. The project tested both n-type and p-type SiO 2 /poly-Si passivated contacts grown by thermal oxidation and plasma enhanced chemical vapor deposition (PECVD) of the poly-Si layer on DWP with varying wafer resistivities. Both deposition techniques are industry standards and thus economically viable methods for commercializing the contacts. The results indicated that both n-type and p-type poly-Si passivated contacts can be formed on polycrystalline DWP wafers, but implied open-circuit voltages (i Voc ) were limited to below 0.65 mV (compared with ~ 730 mV on n-Cz wafers). Diffusion of H to the Si/SiO 2 /poly-Si interface was key to obtaining high i Voc values. In this study, H was diffused from a high-temperature SiN x layer deposited over the poly-Si layer during a high-temperature firing step, similar to one used for screen printed metals. The study concluded that poly-Si passivated contacts on DWP wafers passivated the surface of the wafers as well as PERC passivated surfaces, which use a less expensive dielectric layer stack. The project showed that Direct Wafer Product wafers grown by CubicPV could produce high i Voc values (~0.647 mV), which could produce a cell over 20% efficient with proper processing and metallization. These cells, though not economically viable in 2024 as a stand-alone cell, could be integrated with a wide-bandgap top solar cell to form a two-junction tandem cell that could be viable under certain circumstances. This is because the bottom cell of a 30%, two-terminal tandem only needs to be a 20% cell under one-sun conditions. Thus, the DWP could be an ideal low-cost wafer for tandems. The project also revealed that a TOPCon type cell could be formed on a p-type DWP wafer using a P-diffused emitter and a p-type poly-Si contact. In fact, the p-type version of the poly-Si contact out-performed the n-type version for a variety of wafer resistivities, from highly doped to lowly doped. This curiosity requires more work to understand because on Cz wafers, the n-type poly-Si contact is of much higher quality than the p-type version.

14 SOLAR ENERGY↗
NASA NTRS2003

Wafer-Level Membrane-Transfer Process for Fabricating MEMS

A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

Yang, Eui-Hyeok↗
DOE OSTI2020

Technoeconomic Analysis of Photovoltaics Module Manufacturing with Thin Silicon Wafers

Reducing silicon usage by adopting thinner wafers can significantly reduce capital expenditure (capex) and cost, and thus accelerate the growth of manufacturing capacity and deployment. In this work, we evaluated potential benefits of thin Si wafers for current and future PV modules. We apply a technoeconomic framework that couples bottom-up cost model, and a cash-flow growth model to analyze PV modules with thin wafers. First, we show that, comparing the current PERC with 160 um thick wafers to the high-efficiency concept with 50 um thin wafers, the capex is reduced from 0.39 to 0.2 $/(W/year) while the cost is from 0.32 to 0.2 $/W. Second, the potential of accelerated deployment is analyzed for the highefficiency thin wafer concept. We found the significant advantages of higher growth rate (~20% relative) and higher deployment plateau (~3 times) than the current PERC modules. modules with thin wafers. First, we show that, comparing the current PERC with 160 um thick wafers to the high-efficiency concept with 50 um thin wafers, the capex is reduced from 0.39 to 0.2 $/(W/year) while the cost is from 0.32 to 0.2 $/W. Second, the potential of accelerated deployment is analyzed for the highefficiency thin wafer concept. We found the significant advantages of higher growth rate (~20% relative) and higher deployment plateau (~3 times) than the current PERC modules.

14 SOLAR ENERGY↗
NASA NTRS1994

P/N InP solar cells on Ge wafers

Indium phosphide (InP) P-on-N one-sun solar cells were epitaxially grown using a metalorganic chemical vapor deposition process on germanium (Ge) wafers. The motivation for this work is to replace expensive InP wafers, which are fragile and must be thick and therefore heavy, with less expensive Ge wafers, which are stronger, allowing use of thinner, lighter weight wafers. An intermediate InxGs1-xP grading layer starting as In(0.49)Ga(0.51) at the GaAs-coated Ge wafer surface and ending as InP at the top of the grading layer (backside of the InP cell) was used to attempt to bend some of the threading dislocations generated by lattice-mismatch between the Ge wafer and InP cell so they would be harmlessly confined in this grading layer. The best InP/Ge cell was independently measured by NASA-Lewis with a one-sun 25 C AMO efficiently measured by NASA-Lewis with a one-circuit photocurrent 22.6 mA/sq cm. We believe this is the first published report of an InP cell grown on a Ge wafer. Why get excited over a 9 percent InP/Ge cell? If we look at the cell weight and efficiency, a 9 percent InP cell on an 8 mil Ge wafer has about the same cell power density, 118 W/kg (BOL), as the best InP cell ever made, a 19 percent InP cell on an 18 mil InP wafer, because of the lighter Ge wafer weight. As cell panel materials become lighter, the cell weight becomes more important, and the advantage of lightweight cells to the panel power density becomes more important. In addition, although InP/Ge cells have a low beginning-of-life (BOL) efficiency due to dislocation defects, the InP/Ge cells are very radiation hard (end-of-life power similar to beginning-of-life). We have irradiated an InP/Ge cell with alpha particles to an equivalent fluence of 1.6 x 10(exp 16) 1 MeV electrons/sq cm and the efficiency is still 83 percent of its BOL value. At this fluence level, the power output of these InP/Ge cells matches the GaAs/Ge cell data tabulated in the JPL handbook. Data are presented indicating InP/Ge has more power output than GaAs/Ge cells at fluences in excess of this value.

Wojtczuk, Steven↗