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At least 37 records · Page 2

On the Ambiguity of Using Isc for Analyzing Suns-Voc Data on Modules

In standard silicon solar modules, cells are strung in series with bypass diodes incorporated to reduce the effects of shading. When all of the strings are partially shaded the measured short circuit current is affected and the Isc of the module will be equal to that of the lowest current cell in the least shadowed string. In bifacial modules the ability to assess losses due to shading is especially important. This paper advocates an alternative approach to converting the raw suns-voc data to pseudo IV data in modules where shading may be affecting the suns-voc curve results.

41 EE - Solar Energy Technologies Office (EE-4S)↗

Impact of undoped substrates on high performance silicon solar cells

Today's highest-efficiency silicon solar cells typically operate near the threshold between low-level and high-level injection. It is not well understood if pushing further into a regime in which the cell operating point is solidly in high-level injection at all times of the day has further benefits for the solar cell performance. From a reliability perspective, cells fabricated on lower doped silicon have a larger breakdown voltage. This advantage can affect the design of modules allowing higher voltages and a relaxation of the number of bypass diodes needed. In this project, we present a comprehensive assessment, both experimental and using simulation, of how bulk resistivity, light intensity, and operation temperature impact the performance of the silicon solar cell. This work incorporates a comprehensive device physics analysis assisted by numerical simulation. The source code is now available under General Public License (GPL3), and to further leverage the findings of this project and outreach people outside of the scientific community, we are working with www.pveducation.org (which receives >1 million visitors a year) to create interactive content using our simulation results. The simulation results indicate that high bulk resistivity wafers (>>10 Ωcm) require bulk Shockley-Read-Hall (SRH) lifetimes in the millisecond range to outperform wafers with standard bulk resistivities (<10 Ωcm). Additionally, above bulk resistivities of 10 Ωcm (the exact value depends on the bulk characteristics of the wafer), the cell efficiency is weakly dependent on the bulk resistivity. As a result, ingot manufactures may have an opportunity to further reduce wafer cost by growing higher resistivity ingots that are more tolerant to resistivity variations. This project is particularly relevant today, as solar cell architectures with improved surface passivation and milliseconds lifetimes wafers are commercially available, leveraging potential benefits of using higher bulk resistivities. Outside of interdigitated back contact (IBC) cell, reported studies on high resistivity silicon (>100 Ωcm) are very limited. To the best of our knowledge, this project provides for the first-time experimental insight on solar cells fabricated on wafers with bulk resistivities up to several thousand Ωcm, delivering a comprehensive vision of their performance under real-world temperature and light intensity operation conditions. We manufactured and characterized solar cells with bulk resistivities in the range of 1 Ωcm to >15k Ωcm. Under standard testing conditions (STC), we measured solar cells efficiencies over 20% over the entire range of bulk resistivities, using our baseline cell processing. To evaluate the cell performance in real-world operation conditions, the solar cells were measured at different temperatures (25-80°C) and at different light intensities (0.1-1 suns). The measurements show that the bulk resistivity does not impact the solar cell response to temperature and light intensity. Similar thermal coefficients (TC) were measured for standard and high bulk resistivities, and they are comparable with the TC values reported in the literature for standard bulk resistivities <10 Ωcm. After light soaking, the solar cell didn’t show signs of light-induced degradation (LID). This result was expected since n-type float zone (FZ) wafers were used in this work, i.e. low traces of boron and low concentration of oxygen (oxygen is typically found in the seed end of Czochralski (CZ) ingots). We measured for high bulk resistivities (>10 Ωcm) extremely high breakdown voltages (>1000V). In conclusion, the insight provided by this project can positively impact the levelized cost of energy (LCOE) of the photovoltaic systems through its effect on cell and ingot manufacturing yield, silicon cell power output, and module reliability.

14 SOLAR ENERGY↗

Gate assisted turn-off thyristor with cathode shunts and dynamic gate

A 1,000-V, 200-A gate-assisted turn-off thyristor (GATT) is described, whose design features include an interdigitated shunted cathode, a dynamic gate, a means for optimizing the carrier lifetime level, and a bypass diode. The device physics of gate-assisted turn-off are reviewed. Based on this, improvements in the design are described. It is shown that a prime failure mode can be eliminated and that the gate-assist signal voltage can be substantially decreased by employing a shunted cathode emitter. The test data show excellent turn-on characteristics due to the dynamic gate and the long perimeter of the edge of the main cathode. Turn-off times as short as 3 microsec are obtained. The combination of controlling the carrier lifetime with a precisely controlled and easily variable irradiation dose of high energy electrons with gate assist current provides for simple, precision tailoring of the device characteristics to the intended application.

Schlegel, E. S.↗

Reliability and performance experience with flat-plate photovoltaic modules

Statistical models developed to define the most likely sources of photovoltaic (PV) array failures and the optimum method of allowing for the defects in order to achieve a 20 yr lifetime with acceptable performance degradation are summarized. Significant parameters were the cost of energy, annual power output, initial cost, replacement cost, rate of module replacement, the discount rate, and the plant lifetime. Acceptable degradation allocations were calculated to be 0.0001 cell failures/yr, 0.005 module failures/yr, 0.05 power loss/yr, a 0.01 rate of power loss/yr, and a 25 yr module wear-out length. Circuit redundancy techniques were determined to offset cell failures using fault tolerant designs such as series/parallel and bypass diode arrangements. Screening processes have been devised to eliminate cells that will crack in operation, and multiple electrical contacts at each cell compensate for the cells which escape the screening test and then crack when installed. The 20 yr array lifetime is expected to be achieved in the near-term.

Ross, R. G., Jr.↗

Hot-spot heating in central-station arrays

Hot spot tests performed on the Sacramento Municipal Utility District (SMUD) verificaton array show that current imbalance occurs, resulting in significant hot spot heating. One cause of current imbalance is differences in the average shunt resistances of parallel cell strings due to cell shunt resistance variations. In depth hot spot tests are performed on the verification array with bypass diodes. The tests had several objectives: (1) a comparison of hot spot temperatures achieved under field conditions with those obtained with the present laboratory hot spot test using similar modules; (2) an assessment of current imbalance versus cross tie frequency; and (3) an assessment of different shadow patterns and shadow densities. Instrumented modules are used to vary the number of cross ties and to measure the test-cell current and back-bias voltage. The widths, lengths, and densities of the shadows are varied to maximize the back bias voltage at maximum power current. An infrared camera is used to indicate the existence of hot spots and estimate temperature increases in conjunction with thermocouples. The results of these hot spot tests indicate a sensitivity of back bias heating to the shadow size (amount of cell coverage) and density.

Gonzalez, C. C.↗

Source circuit design considerations

The cost of several circuit configurations for large (5MW) array fields were investigated to assess the relative costs of high and low voltage configurations. Three source circuit NOC voltages were evaluated: 400V (ungrounded), 800V (+ or 400V center grounded), and 2000V (+ or - 1000V center grounded). Four source circuit configurations were considered for each of the three NOC voltages. The configurations correspond to source circuit currents of 15, 30, 45, and 60 amperes, respectively. Conceptual layouts for 5MW building blocks for each of the above configurations were developed. The designs were optimized to minimize BOS electrical and structural costs. Only the BOS electrical costs were evaluated. The designs were broken down into the following elements for cost: (1) basic source circuit intermodule wiring, bypass diodes and associated hardware, source circuit to J-Box wiring, etc; (2) J-Box blocking diodes, varistors, heat sinks, and housing; (3) disconnects source circuit disconnects, fuses, and housing; (4) bus cabling J-Box to PCU interface wiring, and trenching; (5) interface bus bar, group disconnects, and fuses; and (6) fault detection shunts, signal wire, electronics, and alarm. It is concluded that high voltage low current circuits are not economical, at higher currents high and low voltage circuit costs approach each other, high voltage circuits are not likely to offer near term advantage, and development work/manufacturer stimulation is needed to develop low cost high voltage hardware.

Noel, G. T.↗

Hot-spot heating susceptibility due to reverse bias operating conditions

Because of field experience (indicating that cell and module degradation could occur as a result of hot spot heating), a laboratory test was developed at JPL to determine hot spot susceptibility of modules. The initial hot spot testing work at JPL formed a foundation for the test development. Test parameters are selected as follows. For high shunt resistance cells, the applied back bias test current is set equal to the test cell current at maximum power. For low shunt resistance cells, the test current is set equal to the cell short circuit current. The shadow level is selected to conform to that which would lead to maximum back bias voltage under the appropriate test current level. The test voltage is determined by the bypass diode frequency. The test conditions are meant to simulate the thermal boundary conditions for 100 mW/sq cm, 40C ambient environment. The test lasts 100 hours. A key assumption made during the development of the test is that no current imbalance results from the connecting of multiparallel cell strings. Therefore, the test as originally developed was applicable for single string case only.

Gonzalez, C. C.↗

Crystalline-silicon photovoltaics summary module design and reliability

The evolution of the design and reliability of solar modules was described. Design requirements involved 14 different considerations, including residential building and material electrical codes, wind-loading, hail impact, operating temperature levels, module flammability, and interfaces for both the array structure and the operation of the system. Reliability research involved in diverse investigations including glass-fracture strength, soiling levels, electrochemical corrosion, and bypass-diode qualification tests. Based on these internationally recognized studies, performance assessments, and failure analyses, the Flat-plate Solar Array Project in its 11-year duration served to nuture the development of 45 different solar module designs from 15 PV manufacturers.

Ross, R. G., Jr.↗

Concentrator hot-spot testing, phase 1

Results of a study to determine the hot-spot susceptibility of concentrator cells, to provide a hot-spot qualification test for concentrator modules, and to provide guidelines for reducing hot-spot susceptibility are presented. Hot-spot heating occurs in a photovoltaic module when the short-circuit current of a cell is lower than the string operating current forcing the cell into reverse bias with a concurrent power dissipation. Although the basis for the concentrator module hot-spot qualification test is the test developed for flat-plate modules, issues, such as providing cell illumination, introduce additional complexities into the testing procedure. The same general guidelines apply for protecting concentrator modules from hot-spot stressing as apply to flat-plate modules. Therefore, recommendations are made on the number of bypass diodes required per given number of series cells per module or source circuit. In addition, a new method for determining the cell temperature in the laboratory or in the field is discussed.

Gonzalez, C. C.↗

Hot-spot durability testing of amorphous cells and modules

This paper discusses the results of a study to determine the hot-spot susceptibility of amorphous-silicon (a-Si) cells and modules, and to provide guidelines for reducing that susceptibility. Amorphous-Si cells are shown to have hot-spot susceptibility levels similar to crystalline-silicon (C-Si) cells. This premise leads to the fact that the same general guidelines must apply to protecting a-Si cells from hot-spot stressing that apply to C-Si cells. Recommendations are made on ways of reducing a-Si module hot-spot susceptibility including the traditional method of using bypass diodes and a new method unique to thin-film cells, limiting the string current by limiting cell area.

Gonzalez, Charles↗

Hot-spot qualification testing of concentrator modules

Results of a study to determine the hot-spot susceptibility of concentrator cells, to provide a hot-spot qualification test for concentrator modules, and to provide guidelines for reducing hot-spot susceptibility are presented. Hot-spot heating occurs in a photovoltaic module when the short-circuit current of a cell is lower than the string operating current, forcing the cell into reverse bias with a concurrent power dissipation. Although the basis for the concentrator-module hot-spot qualification test is the test developed for flat-plate modules, issues such as providing cell illumination introduce additional complexities into the testing procedure. The results indicate that the same general guidelines apply to protecting concentrator modules from hot-spot stressing as apply to flat-plate modules, and recommendations are made on the number of bypass diodes required per given number of series cells per module or source circuit. A method for determining the cell temperature in the laboratory or in the field is discussed.

Gonzalez, C. C.↗

Deployable aerospace PV array based on amorphous silicon alloys

The development of the first commercial, ultralight, flexible, deployable, PV array for aerospace applications is discussed. It is based on thin-film, amorphous silicon alloy, multijunction, solar cells deposited on a thin metal or polymer by a proprietary, roll-to-roll process. The array generates over 200 W at AM0 and is made of 20 giant cells, each 54 cm x 29 cm (1566 sq cm in area). Each cell is protected with bypass diodes. Fully encapsulated array blanket and the deployment mechanism weigh about 800 and 500 g, respectively. These data yield power per area ratio of over 60 W/sq m specific power of over 250 W/kg (4 kg/kW) for the blanket and 154 W/kg (6.5 kg/kW) for the power system. When stowed, the array is rolled up to a diameter of 7 cm and a length of 1.11 m. It is deployed quickly to its full area of 2.92 m x 1.11 m, for instant power. Potential applications include power for lightweight space vehicles, high altitude balloons, remotely piloted and tethered vehicles. These developments signal the dawning of a new age of lightweight, deployable, low-cost space arrays in the range from tens to tens of thousands of watts for near-term applications and the feasibility of multi-100 kW to MW arrays for future needs.

Hanak, Joseph J.↗

Electrical power system WP-04

Viewgraphs on Space Station Freedom Electrical Power System (EPS) WP-40 are presented. Topics covered include: key EPS technical requirements; photovoltaic power module systems; solar array assembly; blanket containment box and box positioning subassemblies; solar cell; bypass diode assembly; Kapton with atomic oxygen resistant coating; sequential shunt unit; gimbal assembly; energy storage subsystem; thermal control subsystem; direct current switching unit; integrated equipment assembly; PV cargo element; PMAD system; and PMC and AC architecture.

Nored, Donald L.↗

Safety Performance of Small Lithium-Ion Cells in High Voltage Batteries

Topics covered include: Small-cell EAPU work done by NASA-JSC & COM DEV; Looking at safety features (short circuit protection - PTCs); Early tests showed that long strings do not withstand short circuit; a) Some PTCs experience large negative voltages; b) Destructive results. Solution: group cells into shorter substrings, with bypass diodes Work included: a) Tests with single cells shorted; b) Tests with single cells with imposed-negative voltages; c) 6s, 7s and 8s string shorts; and d) Tests with protection scheme in place, on 12s and 41s x 5p.

Cowles, Philip R.↗

Integrated Bypass Battery for ReverseBias Protection

When a single solar cell of a series-connect string is placed in shadow, the entire array current is forced through that cell in reverse bias. Reverse bias current can lead to "hot-spot" heating, where the power produced by the unshadowed cells is dissipated as heat in the shadowed cell. Since occasional shadows are unavoidable in most applications, most solar arrays include shadow protection to prevent damage. In current practice, shadow protection is done with a "bypass diode" on each cell, to shunt the reverse bias current if a cell is shadowed. A new method of reverse bias protection is to use an Integral thin-film battery to provide voltage in the case of a shadowed cell. In this case, the shadowed cell continues to provide voltage during the transient shadow.

Landis, Geoffrey A,↗

Reverse bias protected solar array with integrated bypass battery

A method for protecting the photovoltaic cells in a photovoltaic (PV) array from reverse bias damage by utilizing a rechargeable battery for bypassing current from a shaded photovoltaic cell or group of cells, avoiding the need for a bypass diode. Further, the method mitigates the voltage degradation of a PV array caused by shaded cells.

Landis, Geoffrey A↗

Design Safety Used in NASA's Human-rated Primary Lithium Batteries

Single cell tests were benign for external short, inadvertent charge and overdischarge into reversal up to 4.5 A. At lower current loads cells die (may be due to excessive dendrite formation) benignly. String level external short circuits lead to an unbalanced overdischarge, with one cell going into reversal. The result is catastrophic violent venting. Unbalanced string overdischarges at different currents causes catastrophic violent venting also. Heat-to-vent is very dramatic displaying violent venting Simulated internal short is also catastrophic and displays violent venting. Battery is not UL-rated; hence does not have dual-fault tolerance or tolerance to inherent cell tolerance to failures Battery Design for NASA JSC's human-rated application for use on ISS was changed to include two bypass diodes per cell to provide for two-failure tolerance to overdischarge into reversal (and external short) hazards.

Jeevarajan, J.↗

Bypass rod transfers heat developed in thermionic diode

In a thermionic diode, a cesium tube joining the emitter-collector area and the cesium reservoir is fitted with a copper bypass rod held in place by two standoff brackets. The rod transfers heat from the emitter-collector to the reservoir without going through the ceramic seal structure which surrounds the cesium tube and cannot sustain large temperature gradients.

Lazaridis, L. J.↗