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At least 37 records · Page 2

High data rate Reed-Solomon encoding and decoding using VLSI technology

Presented as an implementation of a Reed-Solomon encode and decoder, which is 16-symbol error correcting, each symbol is 8 bits. This Reed-Solomon (RS) code is an efficient error correcting code that the National Aeronautics and Space Administration (NASA) will use in future space communications missions. A Very Large Scale Integration (VLSI) implementation of the encoder and decoder accepts data rates up 80 Mbps. A total of seven chips are needed for the decoder (four of the seven decoding chips are customized using 3-micron Complementary Metal Oxide Semiconduction (CMOS) technology) and one chip is required for the encoder. The decoder operates with the symbol clock being the system clock for the chip set. Approximately 1.65 billion Galois Field (GF) operations per second are achieved with the decoder chip set and 640 MOPS are achieved with the encoder chip.

Miller, Warner↗

VLSI Reed Solomon decoder design

A Reed Solomon code is a highly efficient error correcting code that NASA will use in future space communication missions. A VLSI implementation of the decoder is presented that accepts data rates of 80 Mbits/second. A total of seven chips are needed and operate with the symbol clock being the system clock for the chip set. Approximately 1.65 billion Galois Field operations per second are achieved with this chip set.

Maki, Gary K.↗

Test chips and ASIC qualification

A test chip set being developed to aid in the qualification of spaceborne Application Specific Integrated Circuits (ASICs) is described. The chip set consists of a process monitor for process parameter verification, a fault chip for yield analysis, a reliability chip for ASIC failure rate analysis, and total ionizing dose and single event upset chips for radiation effect analysis. The test structures contained in these chips are discussed along with representative test results.

Buehler, M. G.↗

Application of software technology to a future spacecraft computer design

A study was conducted to determine how major improvements in spacecraft computer systems can be obtained from recent advances in hardware and software technology. Investigations into integrated circuit technology indicated that the CMOS/SOS chip set being developed for the Air Force Avionics Laboratory at Wright Patterson had the best potential for improving the performance of spaceborne computer systems. An integral part of the chip set is the bit slice arithmetic and logic unit. The flexibility allowed by microprogramming, combined with the software investigations, led to the specification of a baseline architecture and instruction set.

Labaugh, R. J.↗

Image processing using Gallium Arsenide (GaAs) technology

The need to increase the information return from space-borne imaging systems has increased in the past decade. The use of multi-spectral data has resulted in the need for finer spatial resolution and greater spectral coverage. Onboard signal processing will be necessary in order to utilize the available Tracking and Data Relay Satellite System (TDRSS) communication channel at high efficiency. A generally recognized approach to the increased efficiency of channel usage is through data compression techniques. The compression technique implemented is a differential pulse code modulation (DPCM) scheme with a non-uniform quantizer. The need to advance the state-of-the-art of onboard processing was recognized and a GaAs integrated circuit technology was chosen. An Adaptive Programmable Processor (APP) chip set was developed which is based on an 8-bit slice general processor. The reason for choosing the compression technique for the Multi-spectral Linear Array (MLA) instrument is described. Also a description is given of the GaAs integrated circuit chip set which will demonstrate that data compression can be performed onboard in real time at data rate in the order of 500 Mb/s.

Miller, Warner H.↗

GPS Position and Heading Circuitry for Ships

Circuit boards that contain radio-frequency (RF) and digital circuitry have been developed by NASA to satisfy a requirement of the Port of Houston Authority for relatively inexpensive Global Positioning System (GPS) receivers that indicate the azimuthal headings as well as the positions of ships. The receiver design utilizes the unique architecture of the Mitel commercial chip-set, which provides for an accurate GPS-based heading-determination device. The major components include two RF front ends (each connected to a separate antenna), a surface-acoustic-wave intermediate-frequency filter between second- and third-stage mixers, a correlator, and a reduced-instruction- set computer. One of the RF front ends operates as a master, the other as a slave. Both RF front ends share a 10-MHz sinusoidal clock oscillator, which provides for more accurate carrier phase measurements between the two antennas. The outputs of the RF front ends are subjected to conventional GPS processing. The commercial-based chip-set design approach provides an inexpensive open architecture GPS platform, which can be used in developing and implementing unique GPS-heading and attitude-determination algorithms for specific applications. The heading is estimated from the GPS position solutions of the two antennas by an algorithm developed specifically for this application. If a third (and preferably a fourth) antenna were added, it would be possible to estimate the attitude of the GPS receiver in three dimensions instead of only its heading in a horizontal plane.

Cooke, Michael P.↗

Lander Lighting Solution to Reduce Pilot & Autonomous Approach Errors

The south pole lighting environment will have harsh low inclination sunlight, making overhead judgement of surface features difficult. Autonomous solutions are great, however, the need for visual monitoring and independent go/no-go decisions remain. Our project proposes that lunar landing systems will be better served by including a powerful landing light system that improves visibility of surfaces from overhead by illuminating the ground at critical distances for the crew to make last minute decisions regarding an approach. The project utilized computer-based optical modeling software to predict requirements for a potential landing light system. The analysis based the lamp prediction from commercially available LED chip sets and lamp optics. The goal was to illustrate a method to raise the surface contrast of a landing site within an acceptable contrast threshold for most camera systems and human observers to recognize hazards that would not be noticed with low inclination sunlight alone. The Apollo lunar landings benefitted from overhead sun or dark conditions. The surface lighting at the Lunar South Pole is a harsh environment where surfaces are lit from a low inclination angle by the sun (from the side). This change in lighting condition precipitates a need for updated lunar landing systems that facilitate improved recognition of landing sites, and thereby increase pilot awareness of landing hazards. The reliance on LIDAR and other autonomous mechanisms alone is risky given the known usage of visual monitoring for operator concurrence on current spacecraft programs and present-day autonomous land-based vehicles. Visual monitoring via cameras or windows requires the surface contrast to be within 3 orders of magnitude for reasonable recognition of objects. Artificial overhead illumination, when sufficiently sized, provides a means to even out contrast problems created by low inclination sunlight, potentially reducing piloting errors. Current vehicle requirements do not specify this type of guidance for the purpose of increasing mission success. An optical ray-trace simulation model was developed in Zemax Optics Studio to predict the best combination of LED power, LED optics, lamp quantity, and lamp location to raise the surface contrast to within 2 orders of magnitude from 3 orders required to further increased visibility and reduce risk. The project considered the following design constraints: potential base diameter of lander, approach distance(s) for a go-no-go decision point (200 meter), solar inclination angle (2-7), lunar surface reflectance (10%), LED chip sets, LED focusing optics, LED power, lamp quantity, lamp locations, and illumination diameter of lunar surface landing zone. The results can be used to establish minimum design constraints for vehicle landing light systems. With a solar inclination angle ranging from 2-7 degrees, the horizontal illumination of the lunar surface is attenuated by about 10% when compared to overhead illumination from the Sun. This modifies the sun's maximum of 130,000 lux to 13,000 lux horizontal illuminance. The artificial lighting system was designed to provide an 18-meter-wide illumination zone, to create viewing clearances around a 6-meter-wide lander. The system provides an average illuminance of 300 lux, meeting the 2 orders of magnitude criteria. The solution utilized modern Chip On Board LEDs, that each utilized 17 watts, with focusing Total Internal Reflection (TIR) lenses. A lighting system of 300 LEDs was arrayed along the "bottom" of a “lander”. With 17 watts per LED, the system is estimated to require 5100 watts. This is a large amount of power, but it would only be needed during critical phases during the landing. LED lighting systems can be dimmed, and it is assumed that as the lander arrives closer to the landing site, the lighting system power can be adjusted as needed to produce the necessary surface illuminance. The designed reduction of contrast improves reliability of safety assessments using real time visible light camera systems and out the window viewing by the crew.

T A Clark↗

The ABC130 barrel module prototyping programme for the ATLAS strip tracker

For the Phase-II Upgrade of the ATLAS Detector [1], its Inner Detector, consisting of silicon pixel, silicon strip and transition radiation sub-detectors, will be replaced with an all new 100% silicon tracker, composed of a pixel tracker at inner radii and a strip tracker at outer radii. The future ATLAS strip tracker will include 11,000 silicon sensor modules in the central region (barrel) and 7,000 modules in the forward region (end-caps), which are foreseen to be constructed over a period of 3.5 years. The construction of each module consists of a series of assembly and quality control steps, which were engineered to be identical for all production sites. In order to develop the tooling and procedures for assembly and testing of these modules, two series of major prototyping programs were conducted: an early program using readout chips designed using a 250 nm fabrication process (ABCN-250) [2,2] and a subsequent program using a follow-up chip set made using 130 nm processing (ABC130 and HCC130 chips). This second generation of readout chips was used for an extensive prototyping program that produced around 100 barrel-type modules and contributed significantly to the development of the final module layout. This paper gives an overview of the components used in ABC130 barrel modules, their assembly procedure and findings resulting from their tests.

47 OTHER INSTRUMENTATION↗

Spacecraft computer technology at Southwest Research Institute

Southwest Research Institute (SwRI) has developed and delivered spacecraft computers for a number of different near-Earth-orbit spacecraft including shuttle experiments and SDIO free-flyer experiments. We describe the evolution of the basic SwRI spacecraft computer design from those weighing in at 20 to 25 lb and using 20 to 30 W to newer models weighing less than 5 lb and using only about 5 W, yet delivering twice the processing throughput. Because of their reduced size, weight, and power, these newer designs are especially applicable to planetary instrument requirements. The basis of our design evolution has been the availability of more powerful processor chip sets and the development of higher density packaging technology, coupled with more aggressive design strategies in incorporating high-density FPGA technology and use of high-density memory chips. In addition to reductions in size, weight, and power, the newer designs also address the necessity of survival in the harsh radiation environment of space. Spurred by participation in such programs as MSTI, LACE, RME, Delta 181, Delta Star, and RADARSAT, our designs have evolved in response to program demands to be small, low-powered units, radiation tolerant enough to be suitable for both Earth-orbit microsats and for planetary instruments. Present designs already include MIL-STD-1750 and Multi-Chip Module (MCM) technology with near-term plans to include RISC processors and higher-density MCM's. Long term plans include development of whole-core processors on one or two MCM's.

Shirley, D. J.↗

Integrated Circuit Immunity

This paper presents a DOD E3 program overview on integrated circuit immunity. The topics include: 1) EMI Immunity Testing; 2) Threshold Definition; 3) Bias Tee Function; 4) Bias Tee Calibration Set-Up; 5) EDM Test Figure; 6) EMI Immunity Levels; 7) NAND vs. and Gate Immunity; 8) TTL vs. LS Immunity Levels; 9) TP vs. OC Immunity Levels; 10) 7805 Volt Reg Immunity; and 11) Seventies Chip Set. This paper is presented in viewgraph form.

Sketoe, J. G.↗

Developing a GUI for the Robotic Test Stand

The introduction of this poster explains the technology behind DUNE’s far and near detectors and how passing neutrinos generate electrons that drift into a wire grid. I then explain how 3 ASICs manage signals received from electron interception. Next, the poster states how COLDATA chips are undergoing quality control by a Robotic Test Stand using a state machine. I further explained how earlier tests were done via a command line script and the necessity to implement a user-friendly Graphical User Interface with new features a command line can’t implement. For the implementation section, tools and methods for implementation are listed such as Python, tkinter, and GitHub as well as how multithreading and queue implementation was necessary for GUI functionality. Then, I elaborated on the GUIs new features. Finally, I explain how the GUI will be distributed across multiple institutions and future changes planned for the GUI. Photos of the RTS, far detector cave, diagram of anode assembly plane, COLDATA chips, set up tab, result tab, and legacy command line interface are shown.

Gutierrez Villanueva, Jaziel [DuPage Coll.]↗

Finite element computation with parallel VLSI

This paper describes a parallel processing computer consisting of a 16-bit microcomputer as a master processor which controls and coordinates the activities of 8086/8087 VLSI chip set slave processors working in parallel. The hardware is inexpensive and can be flexibly configured and programmed to perform various functions. This makes it a useful research tool for the development of, and experimentation with parallel mathematical algorithms. Application of the hardware to computational tasks involved in the finite element analysis method is demonstrated by the generation and assembly of beam finite element stiffness matrices. A number of possible schemes for the implementation of N-elements on N- or n-processors (N is greater than n) are described, and the speedup factors of their time consumption are determined as a function of the number of available parallel processors.

Mcgregor, J.↗

Stanford Hardware Development Program

Architectures for high performance, digital signal processing, particularly for high resolution, wide band spectrum analysis were developed. These developments are intended to provide instrumentation for NASA's Search for Extraterrestrial Intelligence (SETI) program. The real time signal processing is both formal and experimental. The efficient organization and optimal scheduling of signal processing algorithms were investigated. The work is complemented by efforts in processor architecture design and implementation. A high resolution, multichannel spectrometer that incorporates special purpose microcoded signal processors is being tested. A general purpose signal processor for the data from the multichannel spectrometer was designed to function as the processing element in a highly concurrent machine. The processor performance required for the spectrometer is in the range of 1000 to 10,000 million instructions per second (MIPS). Multiple node processor configurations, where each node performs at 100 MIPS, are sought. The nodes are microprogrammable and are interconnected through a network with high bandwidth for neighboring nodes, and medium bandwidth for nodes at larger distance. The implementation of both the current mutlichannel spectrometer and the signal processor as Very Large Scale Integration CMOS chip sets was commenced.

Peterson, A.↗

Onboard high data rate signal processing and storage

The objective is to advance the state of the art in onboard image data processing and storage through the use of advanced gallium arsenide integrated circuit technology. Viewgraphs are given on research and development efforts, an adaptive programmable processor chip set, design characteristics of an eight bit general processor, and a density comparison of silicon and gallium arsenide integrated circuits.

Miller, Warner H.↗

High speed synchronizer card utilizing VLSI technology

A generic synchronizer card capable of providing standard NASA communication block telemetry frame synchronization and quality control was fabricated using VLSI technology. Four VLSI chip sets are utilized to shrink all the required functions into a single synchronizer card. The application of VLSI technology to telemetry systems resulted in an increase in performance and a decrease in cost and size.

Speciale, Nicholas↗

The Xpress Transfer Protocol (XTP): A tutorial (short version)

The Xpress Transfer Protocol (XTP) is a reliable, light weight transfer layer protocol. Current transport layer protocols such as DoD's Transmission Control Protocol (TCP) and ISO's Transport Protocol (TP) were not designed for the next generation of high speed, interconnected reliable networks such as fiber distributed data interface (FDDI) and the gigabit/second wide area networks. Unlike all previous transport layer protocols, XTP is being designed to be implemented in hardware as a VLSI chip set. By streamlining the protocol, combining the transport and network layers, and utilizing the increased speed and parallelization possible with a VLSI implementation, XTP will be able to provide the end-to-end data transmission rates demanded in the high speed networks without compromising reliability and functionality. This tutorial briefly describes the operation of the XTP protocol and in particular, its error, flow and rate control; inter-networking addressing mechanisms; and multicast support features, as defined in the XTP Protocol Definition Revision 3.4.

Sanders, Robert M.↗

The Xpress Transfer Protocol (XTP): A tutorial (expanded version)

The Xpress Transfer Protocol (XTP) is a reliable, real-time, light weight transfer layer protocol. Current transport layer protocols such as DoD's Transmission Control Protocol (TCP) and ISO's Transport Protocol (TP) were not designed for the next generation of high speed, interconnected reliable networks such as fiber distributed data interface (FDDI) and the gigabit/second wide area networks. Unlike all previous transport layer protocols, XTP is being designed to be implemented in hardware as a VLSI chip set. By streamlining the protocol, combining the transport and network layers and utilizing the increased speed and parallelization possible with a VLSI implementation, XTP will be able to provide the end-to-end data transmission rates demanded in high speed networks without compromising reliability and functionality. This paper describes the operation of the XTP protocol and in particular, its error, flow and rate control; inter-networking addressing mechanisms; and multicast support features, as defined in the XTP Protocol Definition Revision 3.4.

Sanders, Robert M.↗

An adaptive, lossless data compression algorithm and VLSI implementations

This paper first provides an overview of an adaptive, lossless, data compression algorithm originally devised by Rice in the early '70s. It then reports the development of a VLSI encoder/decoder chip set developed which implements this algorithm. A recent effort in making a space qualified version of the encoder is described along with several enhancements to the algorithm. The performance of the enhanced algorithm is compared with those from other currently available lossless compression techniques on multiple sets of test data. The results favor our implemented technique in many applications.

Venbrux, Jack↗