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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1991

A very high speed lossless compression/decompression chip set

A chip is described that will perform lossless compression and decompression using the Rice Algorithm. The chip set is designed to compress and decompress source data in real time for many applications. The encoder is designed to code at 20 M samples/second at MIL specifications. That corresponds to 280 Mbits/second at maximum quantization or approximately 500 Mbits/second under nominal conditions. The decoder is designed to decode at 10 M samples/second at industrial specifications. A wide range of quantization levels is allowed (4...14 bits) and both nearest neighbor prediction and external prediction are supported. When the pre and post processors are bypassed, the chip set performs high speed entropy coding and decoding. This frees the chip set from being tied to one modeling technique or specific application. Both the encoder and decoder are being fabricated in a 1.0 micron CMOS process that has been tested to survive 1 megarad of total radiation dosage. The CMOS chips are small, only 5 mm on a side, and both are estimated to consume less than 1/4 of a Watt of power while operating at maximum frequency.

Venbrux, Jack↗
NASA NTRS1989

A VLSI chip set for real time vector quantization of image sequences

The architecture and implementation of a VLSI chip set that vector quantizes (VQ) image sequences in real time is described. The chip set forms a programmable Single-Instruction, Multiple-Data (SIMD) machine which can implement various vector quantization encoding structures. Its VQ codebook may contain unlimited number of codevectors, N, having dimension up to K = 64. Under a weighted least squared error criterion, the engine locates at video rates the best code vector in full-searched or large tree searched VQ codebooks. The ability to manipulate tree structured codebooks, coupled with parallelism and pipelining, permits searches in as short as O (log N) cycles. A full codebook search results in O(N) performance, compared to O(KN) for a Single-Instruction, Single-Data (SISD) machine. With this VLSI chip set, an entire video code can be built on a single board that permits realtime experimentation with very large codebooks.

Baker, Richard L.↗
NASA NTRS2004

Open-systems Architecture of a Standardized Command Interface Chip-set for Switching and Control of a Spacecraft Power Bus

This viewgraph presentation reviews the architecture of the The CIA-AlA chip-set is a set of mixed-signal ASICs that provide a flexible high level interface between the spacecraft's command and data handling (C&DH) electronics and lower level functions in other spacecraft subsystems. Due to the open-systems architecture of the chip-set including an embedded micro-controller a variety of applications are possible. The chip-set was developed for the missions to the outer planets. The chips were developed to provide a single solution for both the switching and regulation of a spacecraft power bus. The Open-Systems Architecture allows for other powerful applications.

power switch slice (PSS)↗
NASA NTRS2001

InP MMIC Chip Set for Power Sources Covering 80-170 GHz

We will present a Monolithic Millimeter-wave Integrated Circuit (MMIC) chip set which provides high output-power sources for driving diode frequency multipliers into the terahertz range. The chip set was fabricated at HRL Laboratories using a 0.1-micrometer gate-length InAlAs/InGaAs/InP high electron mobility transistor (HEMT) process, and features transistors with an f(sub max) above 600 GHz. The HRL InP HEMT process has already demonstrated amplifiers in the 60-200 GHz range. In this paper, these high frequency HEMTs form the basis for power sources up to 170 GHz. A number of state-of-the-art InP HEMT MMICs will be presented. These include voltage-controlled and fixed-tuned oscillators, power amplifiers, and an active doubler. We will first discuss an 80 GHz voltage-controlled oscillator with 5 GHz of tunability and at least 17 mW of output power, as well as a 120 GHz oscillator providing 7 mW of output power. In addition, we will present results of a power amplifier which covers the full WRIO waveguide band (75-110 GHz), and provides 40-50 mW of output power. Furthermore, we will present an active doubler at 164 GHz providing 8% bandwidth, 3 mW of output power, and an unprecedented 2 dB of conversion loss for an InP HEMT MMIC at this frequency. Finally, we will demonstrate a power amplifier to cover 140-170 GHz with 15-25 mW of output power and 8 dB gain. These components can form a power source in the 155-165 GHz range by cascading the 80 GHz oscillator, W-band power amplifier, 164 GHz active doubler and final 140-170 GHz power amplifier for a stable, compact local oscillator subsystem, which could be used for atmospheric science or astrophysics radiometers.

Ngo, Catherine↗
NASA NTRS2001

InP MMIC chip set for power sources covering 86-170 GHz

We will present a Monolithic Millimeter-wave Integrated Circuit (MMIC) chip set which provides high output-power sources for driving diode frequency multipliers into the terahertz range. The chip set was fabricated at HRL Laboratories using a 0.l-μm gatelength InAI/InGaAs/InP high electron mobility transistor (HEMT) process, and features transistors with an fmax above 600 GHz. The HRL InP HEMT process has already demonstrated amplifiers in the 60-200 GHz range. In this paper, these high frequency HEMTs form the basis for power sources up to 170 GHz.

Ngo, Catherine↗
NASA NTRS2004

Open-systems architecture of a standardized command interface chip-set for switching and control of a spacecraft power bus

The Jet Propulsion Laboratory (JPL) has developed a command interface chip-set that primarily consists of two mixed-signal ASICs'; the Command Interface ASIC (CIA) and Analog Interface ASIC (AIA). The Open-systems architecture employed during the design of this chip-set enables its use as both an intelligent gateway between the system's flight computer and the control, actuation, and activation of the spacecraft's loads, valves, and pyrotechnics respectfully as well as the regulator of the spacecraft power bus. Furthermore, the architecture is highly adaptable and employed fault-tolerant design methods enabling a host of other mission uses including reliable remote data collection. The objective of this design is to both provide a needed flight component that meets the stringent environmental requirements of current deep space missions and to add a new element to a growing library that can be used as a standard building block for future missions to the outer planets.

flight computers↗
NASA NTRS2003

Command Interface ASIC - Analog Interface ASIC Chip Set

A command interface application-specific integrated circuit (ASIC) and an analog interface ASIC have been developed as a chip set for remote actuation and monitoring of a collection of switches, which can be used to control generic loads, pyrotechnic devices, and valves in a high-radiation environment. The command interface ASIC (CIA) can be used alone or in combination with the analog interface ASIC (AIA). Designed primarily for incorporation into spacecraft control systems, they are also suitable for use in high-radiation terrestrial environments (e.g., in nuclear power plants and facilities that process radioactive materials). The primary role of the CIA within a spacecraft or other power system is to provide a reconfigurable means of regulating the power bus, actuating all valves, firing all pyrotechnic devices, and controlling the switching of power to all switchable loads. The CIA is a mixed-signal (analog and digital) ASIC that includes an embedded microcontroller with supporting fault-tolerant switch control and monitoring circuitry that is capable of connecting to a redundant set of interintegrated circuit (I(sup 2)C) buses. Commands and telemetry requests are communicated to the CIA. Adherence to the I(sup 2)C bus standard helps to reduce development costs by facilitating the use of previously developed, commercially available components. The AIA is a mixed-signal ASIC that includes the analog circuitry needed to connect the CIA to a custom higher powered version of the I(sup 2)C bus. The higher-powered version is designed to enable operation with bus cables longer than those contemplated in the I(sup 2)C standard. If there are multiple higher-power I(sup 2)C-like buses, then there must an AIA between the CIA and each such bus. The AIA includes two identical interface blocks: one for the side-A I(sup 2)C clock and data buses and the other for the side B buses. All the AIAs on each side are powered from a common power converter module (PCM). Sides A and B of the I(sup 2)C buses are electrically isolated from each other (see figure). They are also isolated from the CIA by use of transformer coupling of signals between the AIA blocks and the CIA.

Ruiz, Baldes↗
NASA NTRS1993

A High-Density GaAs Gate Array Chip Set for a Deep Space Digital Receiver

The Jet Propulsin Laboratory (JPL), a division of the California Institute of Technology, performs research, development, and related activities for the National Aeronautics and Space Administration (NASA). JPL is NASA's lead center for unmanned exploration of the solar system and beyond.

designing the ASIC's chip set static timing analyz↗
NASA NTRS1990

VLSI chip-set for data compression using the Rice algorithm

A full custom VLSI implementation of a data compression encoder and decoder which implements the lossless Rice data compression algorithm is discussed in this paper. The encoder and decoder reside on single chips. The data rates are to be 5 and 10 Mega-samples-per-second for the decoder and encoder respectively.

Venbrux, J.↗
NASA NTRS1990

CCSDS Reed Solomon VLSI chip set

A highly efficient error correcting code has been selected by NASA as a CCSDS standard: the 16 symbol error correcting Reed Solomon code. A VLSI implementation of this decoder is described in this paper. A total of 4 full custom VLSI chips are needed that correct data in real time at an sustained rate of up to 80 Mbits/second.

Cameron, K.↗
NASA NTRS1991

Low cost high efficiency GaAs monolithic RF module for SARSAT distress beacons

Low cost high performance (5 Watts output) 406 MHz beacons are urgently needed to realize the maximum utilization of the Search and Rescue Satellite-Aided Tracking (SARSAT) system spearheaded in the U.S. by NASA. Although current technology can produce beacons meeting the output power requirement, power consumption is high due to the low efficiency of available transmitters. Field performance is currently unsatisfactory due to the lack of safe and reliable high density batteries capable of operation at -40 C. Low cost production is also a crucial but elusive requirement for the ultimate wide scale utilization of this system. Microwave Monolithics Incorporated (MMInc.) has proposed to make both the technical and cost goals for the SARSAT beacon attainable by developing a monolithic GaAs chip set for the RF module. This chip set consists of a high efficiency power amplifier and a bi-phase modulator. In addition to implementing the RF module in Monolithic Microwave Integrated Circuit (MMIC) form to minimize ultimate production costs, the power amplifier has a power-added efficiency nearly twice that attained with current commercial technology. A distress beacon built using this RF module chip set will be significantly smaller in size and lighter in weight due to a smaller battery requirement, since the 406 MHz signal source and the digital controller have far lower power consumption compared to the 5 watt power amplifier. All the program tasks have been successfully completed. The GaAs MMIC RF module chip set has been designed to be compatible with the present 406 MHz signal source and digital controller. A complete high performance low cost SARSAT beacon can be realized with only additional minor iteration and systems integration.

Petersen, W. C.↗
NASA NTRS1991

An investigation of error correcting techniques for OMV and AXAF

The original objectives of this project were to build a test system for the NASA 255/223 Reed/Solomon encoding/decoding chip set and circuit board. This test system was then to be interfaced with a convolutional system at MSFC to examine the performance of the concantinated codes. After considerable work, it was discovered that the convolutional system could not function as needed. This report documents the design, construction, and testing of the test apparatus for the R/S chip set. The approach taken was to verify the error correcting behavior of the chip set by injecting known error patterns onto data and observing the results. Error sequences were generated using pseudo-random number generator programs, with Poisson time distribution between errors and Gaussian burst lengths. Sample means, variances, and number of un-correctable errors were calculated for each data set before testing.

Ingels, Frank↗
NASA NTRS2000

Visually Lossless Data Compression for Real-Time Frame/Pushbroom Space Science Imagers

A visually lossless data compression technique is currently being developed for space science applications under the requirement of high-speed push-broom scanning. The technique is also applicable to frame based imaging and is error-resilient in that error propagation is contained within a few scan lines. The algorithm is based on a block transform of a hybrid of modulated lapped transform (MLT) and discrete cosine transform (DCT), or a 2-dimensional lapped transform, followed by bit-plane encoding; this combination results in an embedded bit string with exactly the desirable compression rate as desired by the user. The approach requires no unique table to maximize its performance. The compression scheme performs well on a suite of test images typical of images from spacecraft instruments. Flight qualified hardware implementations are in development; a functional chip set is expected by the end of 2001. The chip set is being designed to compress data in excess of 20 Msamples/sec and support quantizations from 2 to 16 bits.

Yeh, Pen-Shu↗