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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 397 records · Page 22
All sourcesNASA NTRSDOE OSTI
NASA NTRS1993

Implementation of ionizing radiation environment requirements for Space Station

Proper functioning of Space Station hardware requires that the effects of high-energy ionizing particles from the natural environment and (possibly) from man-made sources be considered during design. At the Space Station orbit of 28.5-deg inclination and 330-440 km altitude, geomagnetically trapped protons and electrons contribute almost all of the dose, while galactic cosmic rays and anomalous cosmic rays may produce Single Event Upsets (SEUs), latchups, and burnouts of microelectronic devices. Implementing ionizing radiation environment requirements for Space Station has been a two part process, including the development of a description of the environment for imposing requirements on the design and the development of a control process for assessing how well the design addresses the effects of the ionizing radiation environment. We will review both the design requirements and the control process for addressing ionizing radiation effects on Space Station.

Boeder, Paul A.↗
NASA NTRS1992

Charge collection at large angles of incidence

Charge collection exhibited by p-n junctions, which have at least one small dimension, deviates from the geometric assumptions commonly used in SEU (single event upset) testing. The amount of charge collected did not increase with the secant of the angle of incidence. The number of events under the peak in the charge collection spectrum did not decrease as the cosine of the angle of incidence. Both the position of the peak and the number of events under the peak measured at a given angle of incidence depended upon which symmetry axis of the device was chosen to be the axis of rotation.

Mcnulty, P. J.↗
NASA NTRS1992

Charge generation by heavy ions in power MOSFETs, burnout space predictions, and dynamic SEB sensitivity

The transport, energy loss, and charge production of heavy ions in the sensitive regions of IRF 150 power MOSFETs are described. The dependence and variation of transport parameters with ion type and energy relative to the requirements for single event burnout in this part type are discussed. Test data taken with this power MOSFET are used together with analyses by means of a computer code of the ion energy loss and charge production in the device to establish criteria for burnout and parameters for space predictions. These parameters are then used in an application to predict burnout rates in a geostationary orbit for power converters operating in a dynamic mode. Comparisons of rates for different geometries in simulating SEU (single event upset) sensitive volumes are presented.

Stassinopoulos, E. G.↗
NASA NTRS1991

Galileo environmental test and analysis program summary

This paper presents an overview of the Galileo Project's environmental test and analysis program during the spacecraft development phase - October 1978 through launch in October 1989. After describing the top-level objectives of the program, summaries of-the approach, requirements, and margins are provided. Examples of assembly- and system-level test results are given for both the pre-1986 (direct mission) testing and the post-1986 (Venus-Earth-Earth gravity assist mission) testing, including dynamic, thermal, electromagnetic compatibility (EMC), and magnetic. The approaches and results for verifying by analysis that the requirements of certain environments (e.g., radiation, micrometeoroids, and single event upsets) are satisfied are presented. The environmental program implemented on Galileo satisfied the spirit and intent of the requirements imposed by the Project during the spacecraft's development. The lessons learned from the Galileo environmental program are discussed in this paper.

Hoffman, A. R.↗
NASA NTRS1993

Single event test methodology for integrated optoelectronics

A single event upset (SEU), defined as a transient or glitch on the output of a device, and its applicability to integrated optoelectronics are discussed in the context of spacecraft design and the need for more than a bit error rate viewpoint for testing and analysis. A methodology for testing integrated optoelectronic receivers and transmitters for SEUs is presented, focusing on the actual test requirements and system schemes needed for integrated optoelectronic devices. Two main causes of single event effects in the space environment, including protons and galactic cosmic rays, are considered along with ground test facilities for simulating the space environment.

Label, Kenneth A.↗
NASA NTRS1994

Forming Weld Lands On Metal Plates

Forming shoe pounds edge of newly inserted plate workpiece. After many passes of shoe and advances of plate, thick land builds up at edge. Workpiece heated to enable metal to flow without strain hardening. Proposed upset-forming process replaces relatively expensive, time-consuming, and wasteful process in which integral weld lands created by machining metal away from plates everywhere except at lands.

Weddendorf, Bruce↗
NASA NTRS1994

Nonvolatile GaAs Random-Access Memory

Proposed random-access integrated-circuit electronic memory offers nonvolatile magnetic storage. Bits stored magnetically and read out with Hall-effect sensors. Advantages include short reading and writing times and high degree of immunity to both single-event upsets and permanent damage by ionizing radiation. Use of same basic material for both transistors and sensors simplifies fabrication process, with consequent benefits in increased yield and reduced cost.

Katti, Romney R.↗
NASA NTRS1994

Making A D-Latch Sensitive To Alpha Particles

Standard complementary metal oxide/semiconductor (CMOS) D-latch integrated circuit modified to increase susceptibility to single-event upsets (SEU's) (changes in logic state) caused by impacts of energetic alpha particles. Suitable for use in relatively inexpensive bench-scale SEU tests of itself and of related integrated circuits like static random-access memories.

Buehler, Martin G.↗
NASA NTRS1987

Applicative architectures for fault-tolerant multiprocessors

Functional programming frameworks for the design of highly reliable multiprocessor systems are proposed. In contrast to imperative programming environments, a functional environment offers elegant, relatively simple, and efficient solutions to concurrent error detection and recovery problems in multiprocessors. Specific fault tolerance mechanisms for upset exposure, fault containment, secure task assignment, and recovery are developed for a class of applicative multiprocessor architectures. Verification of abstract behavioral characteristics of applicative tasks is used for exposing faults during the execution of tasks. The fault containment mechanism is based on isolation of stack and heap segments of tasks. A protocol for secure task assignment is defined between system components. The architecture permits incremental, distributed, and asynchronous backups of system state. Finally, recovery is accomplished, even in the worst cases, by re-execution of a small number of tasks.

Sharma, Madhumitra↗
NASA NTRS1990

A high speed CCSDS encoder for space applications

This paper reports a VLSI implementation of the CCSDS standard Reed Solomon encoder circuit for the Space Station. The 1.0 micron double metal CMOS chip is 5.9 mm by 3.6 mm, contains 48,000 transistors, operates at a sustained data rate of 320 Mbits/s, and executes 2,560 Mops. The chip features a pin selectable interleave depth of 1 to 8. Block lengths of up to 255 bytes, as well as shortened codes, are supported. The control circuitry uses register cells which are immune to Single Event Upset. In addition, the CMOS process used is reported to be tolerant of over 1 Mrad total dose radiation.

Whitaker, S.↗
NASA NTRS1990

SEU hardening of CMOS memory circuit

This paper reports a design technique to harden CMOS memory circuits against Single Event Upset (SEU) in the space environment. A RAM cell and Flip Flop design are presented to demonstrate the method. The Flip Flop was used in the control circuitry for a Reed Solomon encoder designed for the Space Station.

Whitaker, S.↗
NASA NTRS1993

Test report for single event effects of the 80386DX microprocessor

The Jet Propulsion Laboratory Section 514 Single Event Effects (SEE) Testing and Analysis Group has performed a series of SEE tests of certain strategic registers of Intel's 80386DX CHMOS 4 microprocessor. Following a summary of the test techniques and hardware used to gather the data, we present the SEE heavy ion and proton test results. We also describe the registers tested, along with a system impact analysis should these registers experience a single event upset.

Watson, R. Kevin↗
NASA NTRS1991

NASA Space Engineering Research Center for VLSI systems design

This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

Source record↗
NASA NTRS1991

Experience with custom processors in space flight applications

The Applied Physics Laboratory (APL) has developed a magnetometer instrument for a swedish satellite named Freja with launch scheduled for August 1992 on a Chinese Long March rocket. The magnetometer controller utilized a custom microprocessor designed at APL with the Genesil silicon compiler. The processor evolved from our experience with an older bit-slice design and two prior single chip efforts. The architecture of our microprocessor greatly lowered software development costs because it was optimized to provide an interactive and extensible programming environment hosted by the target hardware. Radiation tolerance of the microprocessor was also tested and was adequate for Freja's mission -- 20 kRad(Si) total dose and very infrequent latch-up and single event upset events.

Fraeman, M. E.↗
NASA NTRS1993

STRV RADMON: An integrated high-energy particle detector

The RADMON (Radiation Monitor) was developed as a compact device with a 4-kbit SRAM particle detector and two p-FET total dose monitors. Thus it can be used as a spacecraft radiation alarm and in situ total dose monitor. This paper discusses the design and calibration of the SRAM for proton, alpha, and heavy ion detection. Upset rates for the RADMON, based on a newly developed space particle flux algorithm, are shown to vary over eight orders of magnitude. On the STRV (Space Technology Research Vehicle) the RADMON's SRAM will be used to detect trapped protons, solar flares, and cosmic rays and to evaluate our ability to predict space results from ground tests.

Buehler, Martin↗
NASA NTRS1993

Test results for SEU and SEL immune memory circuits

Test results for three SEU logic/circuit hardened CMOS memory circuits verify upset and latch-up immunity for two configurations to be in excess of 120 MeV cm(exp 2)/mg using a commercial, non-radiation hardened CMOS process. Test chips from three separate fabrication runs in two different process were evaluated.

Wiseman, D.↗
NASA NTRS1993

Complementary heterojunction FET technology for space application

A 32-bit serial integer multiplier was designed to investigate the yield and performance of complementary heterojunction FET (CHFET) technology. This is the largest reported CHFET logic circuit. The maximum operating frequency was 500 MHz. Very low power dissipation of 3 mW was obtained at 5 MHz operation. Single-event upset (SEU) characteristics of CHFET devices and latches were also measured and indicates the potential for SEU hard circuits for space and military applications.

Larue, George↗
NASA NTRS1993

Design methods for fault-tolerant finite state machines

VLSI electronic circuits are increasingly being used in space-borne applications where high levels of radiation may induce faults, known as single event upsets. In this paper we review the classical methods of designing fault tolerant digital systems, with an emphasis on those methods which are particularly suitable for VLSI-implementation of finite state machines. Four methods are presented and will be compared in terms of design complexity, circuit size, and estimated circuit delay.

Niranjan, Shailesh↗