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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 451 records · Page 25
All sourcesNASA NTRSDOE OSTI
NASA NTRS2012

High-Speed Scanning Interferometer Using CMOS Image Sensor and FPGA Based on Multifrequency Phase-Tracking Detection

A sub-aperture stitching optical interferometer can provide a cost-effective solution for an in situ metrology tool for large optics; however, the currently available technologies are not suitable for high-speed and real-time continuous scan. NanoWave s SPPE (Scanning Probe Position Encoder) has been proven to exhibit excellent stability and sub-nanometer precision with a large dynamic range. This same technology can transform many optical interferometers into real-time subnanometer precision tools with only minor modification. The proposed field-programmable gate array (FPGA) signal processing concept, coupled with a new-generation, high-speed, mega-pixel CMOS (complementary metal-oxide semiconductor) image sensor, enables high speed (>1 m/s) and real-time continuous surface profiling that is insensitive to variation of pixel sensitivity and/or optical transmission/reflection. This is especially useful for large optics surface profiling.

Ohara, Tetsuo↗
NASA NTRS2012

Optimal Dynamic Sub-Threshold Technique for Extreme Low Power Consumption for VLSI

For miniaturization of electronics systems, power consumption plays a key role in the realm of constraints. Considering the very large scale integration (VLSI) design aspect, as transistor feature size is decreased to 50 nm and below, there is sizable increase in the number of transistors as more functional building blocks are embedded in the same chip. However, the consequent increase in power consumption (dynamic and leakage) will serve as a key constraint to inhibit the advantages of transistor feature size reduction. Power consumption can be reduced by minimizing the voltage supply (for dynamic power consumption) and/or increasing threshold voltage (V(sub th), for reducing leakage power). When the feature size of the transistor is reduced, supply voltage (V(sub dd)) and threshold voltage (V(sub th)) are also reduced accordingly; then, the leakage current becomes a bigger factor of the total power consumption. To maintain low power consumption, operation of electronics at sub-threshold levels can be a potentially strong contender; however, there are two obstacles to be faced: more leakage current per transistor will cause more leakage power consumption, and slow response time when the transistor is operated in weak inversion region. To enable low power consumption and yet obtain high performance, the CMOS (complementary metal oxide semiconductor) transistor as a basic element is viewed and controlled as a four-terminal device: source, drain, gate, and body, as differentiated from the traditional approach with three terminals: i.e., source and body, drain, and gate. This technique features multiple voltage sources to supply the dynamic control, and uses dynamic control to enable low-threshold voltage when the channel (N or P) is active, for speed response enhancement and high threshold voltage, and when the transistor channel (N or P) is inactive, to reduce the leakage current for low-leakage power consumption.

Duong, Tuan A.↗
NASA NTRS2010

GaN-Based High Temperature and Radiation-Hard Electronics for Harsh Environments

We develop novel GaN-based high temperature and radiation-hard electronics to realize data acquisition electronics and transmitters suitable for operations in harsh planetary environments. In this paper, we discuss our research on metal-oxide-semiconductor (MOS) transistors that are targeted for 500 (sup o)C operation and >2 Mrad radiation hardness. For the target device performance, we develop Schottky-free AlGaN/GaN MOS transistors, where a gate electrode is processed in a MOS layout using an Al2O3 gate dielectric layer....

AlGaN/GaN↗
NASA NTRS2012

ASIC Readout Circuit Architecture for Large Geiger Photodiode Arrays

The objective of this work was to develop a new class of readout integrated circuit (ROIC) arrays to be operated with Geiger avalanche photodiode (GPD) arrays, by integrating multiple functions at the pixel level (smart-pixel or active pixel technology) in 250-nm CMOS (complementary metal oxide semiconductor) processes. In order to pack a maximum of functions within a minimum pixel size, the ROIC array is a full, custom application-specific integrated circuit (ASIC) design using a mixed-signal CMOS process with compact primitive layout cells. The ROIC array was processed to allow assembly in bump-bonding technology with photon-counting infrared detector arrays into 3-D imaging cameras (LADAR). The ROIC architecture was designed to work with either common- anode Si GPD arrays or common-cathode InGaAs GPD arrays. The current ROIC pixel design is hardwired prior to processing one of the two GPD array configurations, and it has the provision to allow soft reconfiguration to either array (to be implemented into the next ROIC array generation). The ROIC pixel architecture implements the Geiger avalanche quenching, bias, reset, and time to digital conversion (TDC) functions in full-digital design, and uses time domain over-sampling (vernier) to allow high temporal resolution at low clock rates, increased data yield, and improved utilization of the laser beam.

Vasile, Stefan↗
NASA NTRS2012

Compact Autonomous Hemispheric Vision System

Solar System Exploration camera implementations to date have involved either single cameras with wide field-of-view (FOV) and consequently coarser spatial resolution, cameras on a movable mast, or single cameras necessitating rotation of the host vehicle to afford visibility outside a relatively narrow FOV. These cameras require detailed commanding from the ground or separate onboard computers to operate properly, and are incapable of making decisions based on image content that control pointing and downlink strategy. For color, a filter wheel having selectable positions was often added, which added moving parts, size, mass, power, and reduced reliability. A system was developed based on a general-purpose miniature visible-light camera using advanced CMOS (complementary metal oxide semiconductor) imager technology. The baseline camera has a 92 FOV and six cameras are arranged in an angled-up carousel fashion, with FOV overlaps such that the system has a 360 FOV (azimuth). A seventh camera, also with a FOV of 92 , is installed normal to the plane of the other 6 cameras giving the system a > 90 FOV in elevation and completing the hemispheric vision system. A central unit houses the common electronics box (CEB) controlling the system (power conversion, data processing, memory, and control software). Stereo is achieved by adding a second system on a baseline, and color is achieved by stacking two more systems (for a total of three, each system equipped with its own filter.) Two connectors on the bottom of the CEB provide a connection to a carrier (rover, spacecraft, balloon, etc.) for telemetry, commands, and power. This system has no moving parts. The system's onboard software (SW) supports autonomous operations such as pattern recognition and tracking.

Pingree, Paula J.↗
NASA NTRS2012

Prognostics of Power Electronics, Methods and Validation Experiments

Abstract Failure of electronic devices is a concern for future electric aircrafts that will see an increase of electronics to drive and control safety-critical equipment throughout the aircraft. As a result, investigation of precursors to failure in electronics and prediction of remaining life of electronic components is of key importance. DC-DC power converters are power electronics systems employed typically as sourcing elements for avionics equipment. Current research efforts in prognostics for these power systems focuses on the identification of failure mechanisms and the development of accelerated aging methodologies and systems to accelerate the aging process of test devices, while continuously measuring key electrical and thermal parameters. Preliminary model-based prognostics algorithms have been developed making use of empirical degradation models and physics-inspired degradation model with focus on key components like electrolytic capacitors and power MOSFETs (metal-oxide-semiconductor-field-effect-transistor). This paper presents current results on the development of validation methods for prognostics algorithms of power electrolytic capacitors. Particularly, in the use of accelerated aging systems for algorithm validation. Validation of prognostics algorithms present difficulties in practice due to the lack of run-to-failure experiments in deployed systems. By using accelerated experiments, we circumvent this problem in order to define initial validation activities.

Kulkarni, Chetan S.↗
NASA NTRS2013

Miga Aero Actuator and 2D Machined Mechanical Binary Latch

Shape memory alloy (SMA) actuators provide the highest force-to-weight ratio of any known actuator. They can be designed for a wide variety of form factors from flat, thin packages, to form-matching packages for existing actuators. SMA actuators can be operated many thousands of times, so that ground testing is possible. Actuation speed can be accurately controlled from milliseconds to position and hold, and even electronic velocity-profile control is possible. SMA actuators provide a high degree of operational flexibility, and are truly smart actuators capable of being accurately controlled by onboard microprocessors across a wide range of voltages. The Miga Aero actuator is a SMA actuator designed specifically for spaceflight applications. Providing 13 mm of stroke with either 20- or 40-N output force in two different models, the Aero actuator is made from low-outgassing PEEK (polyether ether ketone) plastic, stainless steel, and nickel-titanium SMA wires. The modular actuator weighs less than 28 grams. The dorsal output attachment allows the Aero to be used in either PUSH or PULL modes by inverting the mounting orientation. The SPA1 actuator utilizes commercially available SMA actuator wire to provide 3/8-in. (approx. =.1 cm) of stroke at a force of over 28 lb (approx. = .125 N). The force is provided by a unique packaging of the single SMA wire that provides the output force of four SMA wires mechanically in parallel. The output load is shared by allowing the SMA wire to slip around the output attachment end to adjust or balance the load, preventing any individual wire segment from experiencing high loads during actuation. A built-in end limit switch prevents overheating of the SMA element following actuation when used in conjunction with the Miga Analog Driver [a simple MOSFET (metal oxide semiconductor field-effect transistor) switching circuit]. A simple 2D machined mechanical binary latch has been developed to complement the capabilities of SMA wire actuators. SMA actuators typically perform ideally as latch-release devices, wherein a spring-loaded device is released when the SMA actuator actuates in one direction. But many applications require cycling between two latched states open and closed.

Gummin, Mark A.↗
NASA NTRS2013

Minimal Power Latch for Single-Slope ADCs

Column-parallel analog-to-digital converters (ADCs) for imagers involve simultaneous operation of many ADCs. Single-slope ADCs are well adapted to this use because of their simplicity. Each ADC contains a comparator, comparing its input signal level to an increasing reference signal (ramp). When the ramp is equal to the input, the comparator triggers a latch that captures an encoded counter value (code). Knowing the captured code, the ramp value and hence the input signal are determined. In a column-parallel ADC, each column contains only the comparator and the latches; the ramp and code generation are shared. In conventional latch or flip-flop circuits, there is an input stage that tracks the input signal, and this stage consumes switching current every time the input changes. With many columns, many bits, and high code rates, this switching current can be substantial. It will also generate noise that may corrupt the analog signals. A latch was designed that does not track the input, and consumes power only at the instant of latching the data value. The circuit consists of two S-R (set-reset) latches, gated by the comparator. One is set by high data values and the other by low data values. The latches are cross-coupled so that the first one to set blocks the other. In order that the input data not need an inversion, which would consume power, the two latches are made in complementary polarity. This requires complementary gates from the comparator, instead of complementary data values, but the comparator only triggers once per conversion, and usually has complementary outputs to begin with. An efficient CMOS (complementary metal oxide semiconductor) implementation of this circuit is shown in the figure, where C is the comparator output, D is the data (code), and Q0 and Q1 are the outputs indicating the capture of a zero or one value. The latch for Q0 has a negative-true set signal and output, and is implemented using OR-AND-INVERT logic, while the latch for Q1 uses positive- true signals and is implemented using AND-OR-INVERT logic. In this implementation, both latches are cleared when the comparator is reset. Two redundant transistors are removed from the reset side of each latch, making for a compact layout. CMOS imagers with column-parallel ADCs have demonstrated high performance for remote sensing applications. With this latch circuit, the power consumption and noise can be further reduced. This innovation can be used in CMOS imagers and very-low-power electronics

Hancock, Bruce R.↗
NASA NTRS2013

High-Speed, High-Resolution Time-to-Digital Conversion

This innovation is a series of time-tag pulses from a photomultiplier tube, featuring short time interval between pulses (e.g., 2.5 ns). Using the previous art, dead time between pulses is too long, or too much hardware is required, including a very-high-speed demultiplexer. A faster method is needed. The goal of this work is to provide circuits to time-tag pulses that arrive at a high rate using the hardwired logic in an FPGA - specifically the carry chain - to create what is (in effect) an analog delay line. High-speed pulses travel down the chain in a "wave." For instance, a pulse train has been demonstrated from a 1- GHz source reliably traveling down the carry chain. The size of the carry chain is over 10 ns in the time domain. Thus, multiple pulses will travel down the carry chain in a wave simultaneously. A register clocked by a low-skew clock takes a "snapshot" of the wave. Relatively simple logic can extract the pulses from the snapshot picture by detecting the transitions between logic states. The propagation delay of CMOS (complementary metal oxide semiconductor) logic circuits will differ and/or change as a result of temperature, voltage, age, radiation, and manufacturing variances. The time-to-digital conversion circuits can be calibrated with test signals, or the changes can be nulled by a separate on-die calibration channel, in a closed loop circuit.

Katz, Richard↗
NASA NTRS2013

Millimeter-Wave Localizers for Aircraft-to-Aircraft Approach Navigation

Aerial refueling technology for both manned and unmanned aircraft is critical for operations where extended aircraft flight time is required. Existing refueling assets are typically manned aircraft, which couple to a second aircraft through the use of a refueling boom. Alignment and mating of the two aircraft continues to rely on human control with use of high-resolution cameras. With the recent advances in unmanned aircraft, it would be highly advantageous to remove/reduce human control from the refueling process, simplifying the amount of remote mission management and enabling new operational scenarios. Existing aerial refueling uses a camera, making it non-autonomous and prone to human error. Existing commercial localizer technology has proven robust and reliable, but not suited for aircraft-to-aircraft approaches like in aerial refueling scenarios since the resolution is too coarse (approximately one meter). A localizer approach system for aircraft-to-aircraft docking can be constructed using the same modulation with a millimeterwave carrier to provide high resolution. One technology used to remotely align commercial aircraft on approach to a runway are ILS (instrument landing systems). ILS have been in service within the U.S. for almost 50 years. In a commercial ILS, two partially overlapping beams of UHF (109 to 126 MHz) are broadcast from an antenna array so that their overlapping region defines the centerline of the runway. This is called a localizer system and is responsible for horizontal alignment of the approach. One beam is modulated with a 150-Hz tone, while the other with a 90-Hz tone. Through comparison of the modulation depths of both tones, an autopilot system aligns the approaching aircraft with the runway centerline. A similar system called a glide-slope (GS) exists in the 320-to-330MHz band for vertical alignment of the approach. While this technology has been proven reliable for millions of commercial flights annually, its UHF nature limits its ability to operate beyond the 1-to-2-meter precisions associated with commercial runway width. A prototype ILS-type system operates at millimeter-wave frequencies to provide automatic and robust approach control for aerial refueling. The system allows for the coupling process to remain completely autonomous, as a boom operator is no longer required. Operating beyond 100 GHz provides enough resolution and a narrow enough beamwidth that an approach corridor of centimeter scales can be maintained. Two modules were used to accomplish this task. The first module is a localizer/glide-slope module that can be fitted on a refueling aircraft. This module provides the navigation beams for aligning the approaching aircraft. The second module is navigational receiver fitted onto the approaching aircraft to be re fueled that can detect the approach beams. Since unmanned aircraft have a limited payload size and limited electrical power, the receiver portion was implemented in CMOS (complementary metal oxide semiconductor) technology based on a super-regenerative receiver (SRR) architecture. The SRR achieves mW-level power consumption and chip sizes less than l mm2. While super-regenerative techniques have small bandwidths that limit use in communication systems, their advantages of high sensitivity, low complexity, and low power make them ideal in this situation where modulating tones of less than 1 kHz are used.

Tang, Adrian J.↗
NASA NTRS2014

Investigation of the Semicoa 2N7616 and 2N7425 and the Microsemi 2N7480 for Single-Event Gate Rupture and Single-Event Burnout

Single-event-effect test results for hi-rel total-dose-hardened power MOSFETs are presented in this report. The 2N7616 and the 2N7425 from Semicoa and the 2N7480 from International Rectifier were tested to NASA test condition standards and requirements. The 2N7480 performed well and the data agree with the manufacture's data. The 2N7616 and 2N7425 were entry parts from Semicoa using a new device architecture. Unfortunately, the device performed poorly and Semicoa is withdrawing power MOSFETs from it line due to these data. Vertical metal-oxide-semiconductor field-effect transistors (MOSFETs) are the most commonly used power transistor. MOSFETs are typically employed in power supplies and high current switching applications. Due to the inherent high electric fields in the device, power MOSFETs are sensitive to heavy ion irradiation and can fail catastrophically as a result of single-event gate rupture (SEGR) or single-event burnout (SEB). Manufacturers have designed radiation-hardened power MOSFETs for space applications. See [1] through [5] for more information. The objective of this effort was to investigate the SEGR and SEB responses of two power MOSFETs recently produced. These tests will serve as a limited verification of these parts. It is acknowledged that further testing on the respective parts may be needed for some mission profiles.

Scheick, Leif↗
NASA NTRS2014

Advanced CMOS Radiation Effects Testing and Analysis

Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

cmos↗
NASA NTRS2014

Criticality of Low-Energy Protons in Single-Event Effects Testing of Highly-Scaled Technologies

We report low-energy proton and low-energy alpha particle single-event effects (SEE) data on a 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) latches and static random access memory (SRAM) that demonstrates the criticality of using low-energy protons for SEE testing of highly-scaled technologies. Low-energy protons produced a significantly higher fraction of multi-bit upsets relative to single-bit upsets when compared to similar alpha particle data. This difference highlights the importance of performing hardness assurance testing with protons that include energy distribution components below 2 megaelectron-volt. The importance of low-energy protons to system-level single-event performance is based on the technology under investigation as well as the target radiation environment.

random access memory↗
NASA NTRS2011

An Set-Free, All Digital Controlled Point-of-Load Regulator for Next Generation Power Systems: ADC-POL

This paper presents a digitally controlled programmable point-of-load regulator for next-generation power systems. A novel digital control scheme was designed to minimize single-event effect (SEE)-induced transient effects. By effectively programming the loop transmission, the POL can trade off transient response time with SET robustness. The IC works with 1 to 5.5 V input voltage, 1-4.5V regulated output voltage, high efficiency (peak efficiency at 94%) and power of up to 5 W. The design was fabricated in the AMI i2t100 0.7 mu m complimentary, metal-oxide semiconductor (CMOS) process and characterized with the Jet Propulsion Laboratory (JPL) pulsed laser system.

Digital Signal Processing (DP)↗
NASA NTRS2014

A Highly Sensitive Multi-Element HgCdTe E-APD Detector for IPDA Lidar Applications

An HgCdTe electron avalanche photodiode (e-APD) detector has been developed for lidar receivers, one application of which is integrated path differential absorption lidar measurements of such atmospheric trace gases as CO2 and CH4. The HgCdTe APD has a wide, visible to mid-wave-infrared, spectral response, high dynamic range, substantially improved sensitivity, and an expected improvement in operational lifetime. A demonstration sensor-chip assembly consisting of a 4.3 lm cutoff HgCdTe 4 9 4 APD detector array with 80 micrometer pitch pixels and a custom complementary metal-oxide-semiconductor readout integrated circuit was developed. For one typical array the APD gain was 654 at 12 V with corresponding gain normalized dark currents ranging from 1.2 fA to 3.2 fA. The 4 9 4 detector system was characterized at 77 K with a 1.55 micrometer wavelength, 1 microsecond wide, laser pulse. The measured unit gain detector photon conversion efficiency was 91.1%. At 11 V bias the mean measured APD gain at 77 K was 307.8 with sigma/mean uniformity of 1.23%. The average, noise-bandwidth normalized, system noise-equivalent power (NEP) was 1.04 fW/Hz(exp 1/2) with a sigma/mean of 3.8%. The measured, electronics-limited, bandwidth of 6.8 MHz was more than adequate for 1 microsecond pulse detection. The system had an NEP (3 MHz) of 0.4 fW/Hz(exp 1/2) at 12 V APD bias and a linear dynamic range close to 1000. A gain-independent quantum-limited SNR of 80% of full theoretical was indicative of a gain-independent excess noise factor very close to 1.0 and the expected APD mode quantum efficiency.

NEP↗
NASA NTRS2013

Recent Radiation Test Results for Power MOSFETs

Single-event effect (SEE) and total ionizing dose (TID) test results are presented for various hardened and commercial power metal-oxide-semiconductor field effect transistors (MOSFETs), including vertical planar, trench, superjunction, and lateral process designs.

Lauenstein, Jean-Marie↗
NASA NTRS2015

Precision of FLEET Velocimetry Using High-Speed CMOS Camera Systems

Femtosecond laser electronic excitation tagging (FLEET) is an optical measurement technique that permits quantitative velocimetry of unseeded air or nitrogen using a single laser and a single camera. In this paper, we seek to determine the fundamental precision of the FLEET technique using high-speed complementary metal-oxide semiconductor (CMOS) cameras. Also, we compare the performance of several different high-speed CMOS camera systems for acquiring FLEET velocimetry data in air and nitrogen free-jet flows. The precision was defined as the standard deviation of a set of several hundred single-shot velocity measurements. Methods of enhancing the precision of the measurement were explored such as digital binning (similar in concept to on-sensor binning, but done in post-processing), row-wise digital binning of the signal in adjacent pixels and increasing the time delay between successive exposures. These techniques generally improved precision; however, binning provided the greatest improvement to the un-intensified camera systems which had low signal-to-noise ratio. When binning row-wise by 8 pixels (about the thickness of the tagged region) and using an inter-frame delay of 65 microseconds, precisions of 0.5 meters per second in air and 0.2 meters per second in nitrogen were achieved. The camera comparison included a pco.dimax HD, a LaVision Imager scientific CMOS (sCMOS) and a Photron FASTCAM SA-X2, along with a two-stage LaVision HighSpeed IRO intensifier. Excluding the LaVision Imager sCMOS, the cameras were tested with and without intensification and with both short and long inter-frame delays. Use of intensification and longer inter-frame delay generally improved precision. Overall, the Photron FASTCAM SA-X2 exhibited the best performance in terms of greatest precision and highest signal-to-noise ratio primarily because it had the largest pixels.

Peters, Christopher J.↗