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This work is sponsored by the NASA Electronic Parts and Packaging (NEPP) Program. One of the objectives of this task is to prepare a body of knowledge guideline document summarizing the CMOS technology scaling impact on CMOS parts and parts reliability for space applications. Scaling impact on parts radiation sensitivity is not addressed in this report.
The NASA Electronic Parts and Packaging (NEPP) Program Sensor Technology Commercial Sensor Survey task is geared toward benefiting future NASA space missions with low-cost, short-duty-cycle, visible-wavelength imaging needs. Such applications could include imaging for educational outreach purposes or short surveys of spacecraft, planetary, or lunar surfaces. Under the task, inexpensive, low-power, commercial grade CMOS sensors were surveyed in fiscal year 2007 (FY07), and three sensors were selected and tested for total ionizing dose (TID) and displacement damage dose (DDD) tolerance in fiscal year 2008 (FY08). The selected sensors had to meet selection criteria chosen to support small, low-mass cameras that produce good resolution color images. The commercial CMOS sensors tested under the task in FY08 showed very promising response to typical outreach and survey camera TID and DDD levels. In fiscal year 2009 (FY09), the survey was broadened to include two additional, similar sensor products. This compendium provides results for all radiation testing performed on the Micron and OmniVision sensors that were selected for radiation tolerance testing in FY08 and FY09.
This report is the result of funding by the NASA Electronic Parts and Packaging Program (NEPP) and the combined efforts of members within the Xilinx Radiation Test Consortium (XRTC), sometimes known as the Xilinx Single Event Effects (SEE) Test Consortium. The XRTC is a voluntary association of aerospace entities, including leading aerospace companies, universitie and national laboratories, combining resources to characterize reconfigurable, field programmable gate arrays (FPGAs) for aerospace applications. Previous publications of Virtex-4 radiation results are for commercial (non-epitaxial) devices; see, for example, Refs. 1–5. A notable exception is Ref. 6, which presents XRTC upset measurements of storage elements in the PowerPC405s in the XQR4VFX60. This work represents a continuation of the efforts reported in the “Virtex-4QV Static SEU Characterization Summary” [7]. The contents of this report describe various Single Event Functional Interrupt (SEFI) and Single Event Upset (SEU) modes seen while dynamically exercising the clocked resources within Virtex-4 devices and the corresponding mitigation techniques related to the aforementioned observed SEFI modes.
The National Aeronautics and Space Administration Electronic Parts and Packaging (NEPP) Program has been evaluating state-of-the-art Embedded Passive Technology for the printed circuit board (PCB) industry for the past several years and has conducted its own testing on embedded passive coupons (resistors and capacitors). This document is a progress report of the work performed through fiscal year 2008 by NASA and the Navy to convert an existing PWB (printed wiring board) design to a design that incorporates embedded passive components. The work is being performed through a memorandum of understanding (MOU) between the NEPP Program (NASA) and the Naval Surface Warfare Center (NSWC) Crane Emerging Critical Interconnect Technology (ECIT) Program. NSWC Crane’s ECIT Program has funding to convert two PCB designs from the military and aerospace industry to a PCB design with embedded passives. ECIT will provide a design team that will take a well characterized design and convert it to an embedded design. They will also provide electrical modeling and layout expertise as well as build the PWB in their facility in Indiana. NEPP, through the Jet Propulsion Laboratory (JPL), will assemble any passives deemed not suitable for embedding and the active components and electrically test the new design to the existing (non-embedded) design
This report documents the activities and results of the fiscal year 2009 (FY09) funding for the NASA Electronic Parts and Packaging (NEPP) program for non-volatile memory (NVM) devices. The FY09 task was divided into two main efforts: 1. Development of in-house measurement capability for flash devices 2. Reliability characterization of multi-level vs. single-level flash devices The FY09 NEPP Non Volatile Memory study was organized into these two sections in recognition of the continued and increasing importance of NVM to NASA. All NASA missions use NVM for boot code storage and some limited data archiving. Space-grade NVM has lagged commercial NVM development by many orders of magnitude, however. This gap in density only continues to increase as space-grade memories remain constant in the 1–16 Mbit levels, while commercial flash-based devices shrink in size and double in capacity every 18 months. Commercial flash devices are now at the 32 Gbit level, 10,000 times denser than current NASA NVM. This FY marks the beginning of a significant technological transition in NVM for NASA. The aggressive scaling of commercial NVMs has, as a by-product, made some of the flash devices radiation-tolerant enough to be at least considered for low-level radiation environment missions [Irom 2008]. This NEPP task is focused on understanding the reliability and potential future applications of such highly scaled flash memories.
ComDMFT is a parallel computational package designed to study the electronic structure of correlated quantum materials from first principles. Our approach is based on the combination of first-principles methods and dynamical mean field theories. In version 2.0, we implemented fully-diagrammatic GW+EDMFT from first-principles self-consistently. In this approach, correlated electrons are treated within full GW+EDMFT and the rest are treated within full-GW, seamlessly. Further, this implementation enables the electronic structure calculation of quantum materials with weak, intermediate, and strong electron correlation without prior knowledge of the degree of electron correlation.
Information used in the evaluation of design of Sunkeeper Control's electronic controllers and hydronic packages is discussed. This information includes system performance specifications, a design data brochure, drawings, and qualification and acceptance test procedures.
This invention is an electronically commutated brushless motor controller that incorporates Hall-array sensing in a small, 42-gram package that provides 4096 absolute counts per motor revolution position sensing. The unit is the size of a miniature hockey puck, and is a 44-pin male connector that provides many I/O channels, including CANbus, RS-232 communications, general-purpose analog and digital I/O (GPIO), analog and digital Hall inputs, DC power input (18-90 VDC, 0-l0 A), three-phase motor outputs, and a strain gauge amplifier. This controller replaces air cooling with conduction cooling via a high-thermal-conductivity epoxy casting. A secondary advantage of the relatively good heat conductivity that comes with ultra-small size is that temperature differences within the controller become smaller, so that it is easier to measure the hottest temperature in the controller with fewer temperature sensors, or even one temperature sensor. Another size-sensitive design feature is in the approach to electrical noise immunity. At a very small size, where conduction paths are much shorter than in conventional designs, the ground becomes essentially isopotential, and so certain (space-consuming) electrical noise control components become unnecessary, which helps make small size possible. One winding-current sensor, applied to all of the windings in fast sequence, is smaller and wastes less power than the two or more sensors conventionally used to sense and control winding currents. An unexpected benefit of using only one current sensor is that it actually improves the precision of current control by using the "same" sensors to read each of the three phases. Folding the encoder directly into the controller electronics eliminates a great deal of redundant electronics, packaging, connectors, and hook-up wiring. The reduction of wires and connectors subtracts substantial bulk and eliminates their role in behaving as EMI (electro-magnetic interference) antennas. A shared knowledge by each motor controller of the state of all the motors in the system at 500 Hz also allows parallel processing of higher-level kinematic matrix calculations.
Test probe, in conjunction with standard equipment, tests axial-lead electronic components in their original packages. The probe can be modified to test any electronic component with automatic or nonautomatic equipment.
Advanced hermetic packages developed to house electronic circuits operating at frequencies from 1 to 100 gigahertz and beyond. Signals coupled into and out of packages electromagnetically. Provides circuit packages small, lightweight, rugged, and inexpensive in mass production. Packages embedded in planar microstrip and coplanar waveguide circuits, in waveguide-to-planar and planar-to-waveguide circuitry, in waveguide-to-waveguide circuitry, between radiating (antenna) elements, and between planar transmission lines and radiating elements. Other applications in automotive, communication, radar, remote sensing, and biomedical electronic systems foreseen.
JPL along with other aerospace agencies such as the US Air Force Space Pro-grams and a packaging technology innovator, i3 Electronics, Inc., are evaluating the use of state-of-the-art (SOA) commercial off-the-shelf (COTS) and alternative packaging technologies for future high performance and high reliability space applications. Utilization of SOA COTS technologies have resulted in large scale reduction in electronics volume, weight, power, cost and schedule with outstanding electrical performance and high reliability. We will share JPL’s joint design, architectural approach, alternative substrate materials selection, associated processes, and mission assurance role in identifying reliability and qualification risks, as part of the three year Heterogeneous Packaging/Device Integration effort under the guidance and leadership of JPL’s Mission Assurance Directorate.
The Hydrogen Maser Clock (HMC) project was originally conceived to fly on a reflight of the European Space Agency (ESA) free flying platform, the European Recoverable Carrier (EURECA) that had been launched into space and recovered by NASA's Space Transportation System (STS). A Phase B study for operation of HMC as one of the twelve EURECA payload components was begun in July 1991, and completed a year later. Phase C/D of HMC began in August 1992 and continued into early 1995. At that time ESA decided not to refly EURECA, leaving HMC without access to space. Approximately 80% of the flight support electronics are presently operating the HMC's physics package in a vacuum tank at the Smithsonian Astrophysical Observatory, and are now considered to be well-tested flight electronics. The package will continue to be operated until the end of 1997 or until a flight opportunity becomes avaiable. Appendices: letters and trip report; proceedings of the symposium on frequency standards and metrology; milli-celsius-stability thermal control for an orbiting frequency standard.
This slide presentation reviews packaging challenges and options for electronic parts. The presentation includes information about non-hermetic packages, space challenges for packaging and complex package variations.
Electronic equipment design and packaging with capability of surviving hard impacts in unmanned lunar and planetary landings
Traditional electronics are assembled as a planar arrangement of components on a printed circuit board (PCB) or other type of substrate. These planar assemblies may then be plugged into a motherboard or card cage creating a volume of electronics. This architecture is common in many military and space electronic systems as well as large computer and telecommunications systems and industrial electronics. The individual PCB assemblies can be replaced if defective or for system upgrade. Some applications are constrained by the volume or the shape of the system and are not compatible with the motherboard or card cage architecture. Examples include missiles, camcorders, and digital cameras. In these systems, planar rigid-flex substrates are folded to create complex 3-D shapes. The flex circuit serves the role of motherboard, providing interconnection between the rigid boards. An example of a planar rigid - flex assembly prior to folding is shown. In both architectures, the interconnection is effectively 2-D.
We formulate and implement a spectral method for solving the Schrödinger equation, as it applies to quasi-one-dimensional materials and structures. This allows for computation of the electronic structure of important technological materials such as nanotubes (of arbitrary chirality), nanowires, nanoribbons, chiral nanoassemblies, nanosprings and nanocoils, in an accurate, efficient and systematic manner. Our work is motivated by the observation that one of the most successful methods for carrying out electronic structure calculations of bulk/crystalline systems — the plane-wave method — is a spectral method based on eigenfunction expansion. Our scheme avoids computationally onerous approximations involving periodic supercells often employed in conventional plane-wave calculations of quasi-one-dimensional materials, and also overcomes several limitations of other discretization strategies, e.g., those based on finite differences and atomic orbitals. The basis functions in our method — called helical waves (or twisted waves) — are eigenfunctions of the Laplacian with symmetry adapted boundary conditions, and are expressible in terms of plane waves and Bessel functions in helical coordinates. We describe the setup of fast transforms to carry out discretization of the governing equations using our basis set, and the use of matrix-free iterative diagonalization to obtain the electronic eigenstates. Miscellaneous computational details, including the choice of eigensolvers, use of a preconditioning scheme, evaluation of oscillatory radial integrals and the imposition of a kinetic energy cutoff are discussed. We have implemented these strategies into a computational package called HelicES (Helical Electronic Structure). We demonstrate the utility of our method in carrying out systematic electronic structure calculations of various quasi-one-dimensional materials through numerous examples involving nanotubes, nanoribbons and nanowires. We also explore the convergence properties of our method, and assess its accuracy and computational efficiency by comparison against reference finite difference, transfer matrix method and plane-wave results. We anticipate that our method will find applications in computational nanomechanics and multiscale modeling, for carrying out transport calculations of interest to the field of semiconductor devices, and for the discovery of novel chiral phases of matter that are of relevance to the burgeoning quantum hardware industry.
Review of fast analog/hybrid computer systems, integrated operational amplifiers, electronic mode-control switches, digital attenuators, and packaging techniques