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Results for “CIRCUIT RELIABILITY”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 505 records · Page 28
All sourcesNASA NTRSDOE OSTI
NASA NTRS1983

Laboratory experience with voltage breakdown

Voltage breakdown failures in photovoltaic module electrical insulations lead to loss of entire source circuits and require costly maintenance and replacement. Avoiding such catastrophes requires that modules be designed so that voltage breakdown either never occurs or occurs so rarely that it affects the least life cycle energy costs insignificantly. To achieve this desired balance of cost and reliability, the module design engineer must understand the failure mechanisms and use data on materials and failue rates to suppress or retard them. Recently obtained failure mechanism information, rate data and materials property data and a qualitative model of module failure prediction are presented.

Mon, G. R.↗
NASA NTRS1982

RF model of the distribution system as a communication channel, phase 2. Volume 2: Task reports

Based on the established feasibility of predicting, via a model, the propagation of Power Line Frequency on radial type distribution feeders, verification studies comparing model predictions against measurements were undertaken using more complicated feeder circuits and situations. Detailed accounts of the major tasks are presented. These include: (1) verification of model; (2) extension, implementation, and verification of perturbation theory; (3) parameter sensitivity; (4) transformer modeling; and (5) compensation of power distribution systems for enhancement of power line carrier communication reliability.

Rustay, R. C.↗
NASA NTRS1996

Planar Schottky technology for submillimeter wavelengths

Work carried out in relation to the development of planar integrated Schottky diodes with the aim of increasing the sensitivity, reliability and efficiency of spaceborne heterodyne receivers, is reported. The results of this work include a planar diode mixer at 585 GHz with a total receiver noise temperature of 2,380 K double side band, and planar diode multipliers. The prospects for further integration of circuit elements with the GaAs diodes are discussed.

Crowe, Thomas W.↗
NASA NTRS2012

NASA Tech Briefs, August 2012

Topics covered include: Mars Science Laboratory Drill; Ultra-Compact Motor Controller; A Reversible Thermally Driven Pump for Use in a Sub-Kelvin Magnetic Refrigerator; Shape Memory Composite Hybrid Hinge; Binding Causes of Printed Wiring Assemblies with Card-Loks; Coring Sample Acquisition Tool; Joining and Assembly of Bulk Metallic Glass Composites Through Capacitive Discharge; 670-GHz Schottky Diode-Based Subharmonic Mixer with CPW Circuits and 70-GHz IF; Self-Nulling Lock-in Detection Electronics for Capacitance Probe Electrometer; Discontinuous Mode Power Supply; Optimal Dynamic Sub-Threshold Technique for Extreme Low Power Consumption for VLSI; Hardware for Accelerating N-Modular Redundant Systems for High-Reliability Computing; Blocking Filters with Enhanced Throughput for X-Ray Microcalorimetry; High-Thermal-Conductivity Fabrics; Imidazolium-Based Polymeric Materials as Alkaline Anion-Exchange Fuel Cell Membranes; Electrospun Nanofiber Coating of Fiber Materials: A Composite Toughening Approach; Experimental Modeling of Sterilization Effects for Atmospheric Entry Heating on Microorganisms; Saliva Preservative for Diagnostic Purposes; Hands-Free Transcranial Color Doppler Probe; Aerosol and Surface Parameter Retrievals for a Multi-Angle, Multiband Spectrometer LogScope; TraceContract; AIRS Maps from Space Processing Software; POSTMAN: Point of Sail Tacking for Maritime Autonomous Navigation; Space Operations Learning Center; OVERSMART Reporting Tool for Flow Computations Over Large Grid Systems; Large Eddy Simulation (LES) of Particle-Laden Temporal Mixing Layers; Projection of Stabilized Aerial Imagery Onto Digital Elevation Maps for Geo-Rectified and Jitter-Free Viewing; Iterative Transform Phase Diversity: An Image-Based Object and Wavefront Recovery; 3D Drop Size Distribution Extrapolation Algorithm Using a Single Disdrometer; Social Networking Adapted for Distributed Scientific Collaboration; General Methodology for Designing Spacecraft Trajectories; Hemispherical Field-of-View Above-Water Surface Imager for Submarines; and Quantum-Well Infrared Photodetector (QWIP) Focal Plane Assembly.

Source record↗
NASA NTRS1995

Initial results for the silicon monolithically interconnected solar cell product

This proprietary technology is based on AstroPower's electrostatic bonding and innovative silicon solar cell processing techniques. Electrostatic bonding allows silicon wafers to be permanently attached to a thermally matched glass superstrate and then thinned to final thicknesses less than 25 micron. These devices are based on the features of a thin, light-trapping silicon solar cell: high voltage, high current, light weight (high specific power) and high radiation resistance. Monolithic interconnection allows the fabrication costs on a per watt basis to be roughly independent of the array size, power or voltage, therefore, the cost effectiveness to manufacture solar cell arrays with output powers ranging from milliwatts up to four watts and output voltages ranging from 5 to 500 volts will be similar. This compares favorably to conventionally manufactured, commercial solar cell arrays, where handling of small parts is very labor intensive and costly. In this way, a wide variety of product specifications can be met using the same fabrication techniques. Prototype solar cells have demonstrated efficiencies greater than 11%. An open-circuit voltage of 5.4 volts, fill factor of 65%, and short-circuit current density of 28 mA/sq cm at AM1.5 illumination are typical. Future efforts are being directed to optimization of the solar cell operating characteristics as well as production processing. The monolithic approach has a number of inherent advantages, including reduced cost per interconnect and increased reliability of array connections. These features make this proprietary technology an excellent candidate for a large number of consumer products.

Dinetta, L. C.↗
NASA NTRS1998

Buried Oxide Densification for Low Power, Low Voltage CMOS Applications

Special technology and circuit architecture are of growing interest for implementation of circuits which operate at low supply voltages and consume low power levels without sacrificing performance[1]. Use of thin buried oxide SOI substrates is a primary approach to simultaneously achieve these goals. A significant aspect regarding SIMOX SOI for low voltage, low power applications is the reliability and performance of the thin buried oxide. In addition, when subjected to high total dose irradiation, the silicon islands within the BOX layer of SIMOX can store charges and significantly effect the back channel threshold voltages of devices. Thus, elimination of the islands within the buried oxide (BOX) layer is preferred in order to prevent leakage through these conductive islands and charge build-up within the buried oxide layer. A differential (2-step) ramp rate as applied to full and 100 nm BOX SIMOX was previously reported to play a significant role in the stoichiometry and island formation within the buried layer[2]. This paper focus is on the properties of a thin (120nm) buried oxide as a function of the anneal ramp rate and the temperature of anneal. In this research, we have found an improvement in the buried oxide stoichiometry with the use of a slower, singular ramp rate for specified thin buried oxides, with slower ramp rates and higher temperatures of anneal suggested for reducing the presence of Si islands within the BOX layer.

Allen, L. P.↗
NASA NTRS1987

Fiber optics for controls

The challenge of those involved in control-system hardware development is to accommodate an ever-increasing complexity in aircraft control, while limiting the size and weight of the components and improving system reliability. A technology that displays promise towards this end is the area of fiber optics for controls. The primary advantages of employing optical fibers, passive optical sensors, and optically controlled actuators are weight and volume reduction, immunity from electromagnetic effects, superior bandwidth capabilities, and freedom from short circuits and sparking contacts. Since 1975, NASA Lewis has performed in-house, contract, and grant research in fiber optic sensors, high-temperature electro-optic switches, and fly-by-light control-system architecture. Passive optical sensor development is an essential yet challenging area of work and has therefore received much attention during this period. A major effort to develop fly-by-light control-system technology, known as the Fiber-Optic Control System Integration (FOCSI) program, was initiated in 1985 as a cooperative effort between NASA and DOD. Phase 1 of FOCSI, completed in 1986, was aimed at the design of a fiber-optic integrated propulsion/flight control system. Phase 2, yet to be initiated, will provide subcomponent and system development, and a system engine test. In addition to a summary of the benefits of fiber optics, the FOCSI program, sensor advances, and future directions in the NASA Lewis program will be discussed.

Seng, Gary T.↗
NASA NTRS1993

High Speed Solid State Circuit Breaker

The U.S. Army Research Laboratory, Fort Monmouth, NJ, has developed and is installing two 3.3 MW high speed solid state circuit breakers at the Army's Pulse Power Center. These circuit breakers will interrupt 4160V three phase power mains in no more than 300 microseconds, two orders of magnitude faster than conventional mechanical contact type circuit breakers. These circuit breakers utilize Gate Turnoff Thyristors (GTO's) and are currently utility type devices using air cooling in an air conditioned enclosure. Future refinements include liquid cooling, either water or two phase organic coolant, and more advanced semiconductors. Each of these refinements promises a more compact, more reliable unit.

Podlesak, Thomas F.↗
NASA NTRS1976

Design, processing, and testing of LSI arrays for space station

The applicability of a particular process for the fabrication of large scale integrated circuits is described. Test arrays were designed, built, and tested, and then utilized. A set of optimum dimensions for LSI arrays was generated. The arrays were applied to yield improvement through process innovation, and additional applications were suggested in the areas of yield prediction, yield modeling, and process reliability.

Ipri, A. C.↗
NASA NTRS1995

Development of a 1 kW, 200 C Mapham Inventor

Electronic systems and components are often exposed to high temperature environment in space-based applications, nuclear power facilities, and geothermal energy extraction fields. A key requirement for these systems is, therefore, to withstand the high temperature exposure while maintaining efficient and reliable operation. Efforts were taken to design and develop a high temperature power inverter capable of 200 C operation. A 1 kW, 20 kHz Mapham inverter was designed and evaluated as a function of temperature at different load levels. The inverter system, excluding its input, control, and logic circuits, was characterized at temperatures from ambient to 200 C at 0%, 50%, and 100% resistive loading. With an applied input voltage of 75 VDC, the inverter produced an output of 250 VAC. The results obtained, which indicate good operational characteristics of the inverter up to 200 C, are presented and discussed.

Hammoud, Ahmad↗
NASA NTRS1981

Photovoltaic module and array reliability

Several statistical reliability studies have been conducted in areas of photovoltaic component design covering cell failure, interconnect fatigue, glass breakage and electrical insulation breakdown. This paper integrates the results from these various studies and draws general conclusions relative to optimal reliability features for future modules. The described analysis is based on designing for specified low levels of component failures and then controlling the degrading effects of the failures through the use of fault tolerant circuitry and module replacement. Means of selecting the cost-optimal level of component failures, circuit redundancy, and module replacement are described.

Ross, R. G., Jr.↗
NASA NTRS1989

Inductively-Activated Short-Interval Timer

Timing circuit in pneumatically launched projectile triggers explosive charge in projectile at specified delay after launch. Both power and control signals coupled inductively to timer from stationary launcher circuitry. Eliminates need for direct electrical contacts, which are unreliable and generate sparks that trigger explosive accidentally. Inductive coupling also provides higher reliability in field operation than contacts. Concept useful in such other safety-related applications as remotely or automatically controlling flow of bottled flammable gas.

Wiker, Gordon A.↗
NASA NTRS2007

Improved Sensing Coils for SQUIDs

An improvement in the design and fabrication of sensing coils of superconducting quantum interference device (SQUID) magnetometers has been proposed to increase sensitivity. It has been estimated that, in some cases, it would be possible to increase sensitivity by about half or to reduce measurement time correspondingly. The pertinent aspects of the problems of design and fabrication can be summarized as follows: In general, to increase the sensitivity of a SQUID magnetometer, it is necessary to maximize the magnetic flux enclosed by the sensing coil while minimizing the self-inductance of this coil. It is often beneficial to fabricate the coil from a thicker wire to reduce its self-inductance. Moreover, to optimize the design of the coil with respect to sensitivity, it may be necessary to shape the wire to other than a commonly available circular or square cross-section. On the other hand, it is not practical to use thicker superconducting wire for the entire superconducting circuit, especially if the design of a specific device requires a persistent-current loop enclosing a remotely placed SQUID sensor. It may be possible to bond a thicker sensing-coil wire to thinner superconducting wires leading to a SQUID sensor, but it could be difficult to ensure reliable superconducting connections, especially if the bonded wires are made of different materials. The main idea is to mold the sensing coil in place, to more nearly optimum cross sectional shape, instead of making the coil by winding standard pre-fabricated wire. For this purpose, a thin superconducting wire loop that is an essential part of the SQUID magnetometer would be encapsulated in a form that would serve as a mold. A low-melting-temperature superconducting metal (e.g., indium, tin, or a lead/tin alloy) would be melted into the form, which would be sized and shaped to impart the required cross section to the coil thus formed.

Penanen, Konstantin↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second(Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high- speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗