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Upper bounds on rates of single-event upsets (SEU's) in digital integrated circuits and other electronic devices exposed to anisotropic fluxes of energetic ionizing particles computed by use of improved method. Derived from simplified, worst-case mathematical models of charge-collecting volumes and physical phenomena in electronic devices.
The authors report a design improvement for CMOS static memory circuits hardened against single event upset (SEU) using a recently proposed logic/circuit design technique. This improvement drastically reduces static power consumption, reduces the number of transistors required in a D flip-flop design, and eliminates the possibility of capturing an upset state in the slave section during a clock transition.
This paper reports a design technique to harden CMOS memory circuits against Single Event Upset (SEU) in the space environment. A RAM cell and Flip Flop design are presented to demonstrate the method. The Flip Flop was used in the control circuitry for a Reed Solomon encoder designed for the Space Station.
Test results for three SEU logic/circuit hardened CMOS memory circuits verify upset and latch-up immunity for two configurations to be in excess of 120 MeV cm(exp 2)/mg using a commercial, non-radiation hardened CMOS process. Test chips from three separate fabrication runs in two different process were evaluated.
A single event upset (SEU)-hardened flip-flop has been designed and developed for antifuse Field Programmable Gate Array (FPGA) application. Design and application issues, testability, test methods, simulation, and results are discussed.
The SEU rate in a flash ADC (AD9058) on board a space experiment varied by more than an order of magnitude, depending on the input. A pulsed laser aided in elucidating the reasons, which were found to be the result of the unique design of the AD9058.
The SEU rate in a flash ADC (AD9058) on board a space experiment varied by more than an order of magnitude, depending on the input. A pulsed laser aided in elucidating the reasons, which were found to be the result of the unique design of the AD9058.
We describe heavy ion test results for two new SEU tolerant latches based on transition nand gates, one for single rail asynchronous and the other for dual rail synchronous designs, implemented in AMI 0.5microprocess.
Many papers have presented models for estimating proton SEU cross sections from heavy-ion test data, but all rigorous treatments to date are based on the sensitive volume (SV) model for charge collection.
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This is an independent study to determine the single event destructive and transient susceptibility of the Xilinx Virtex-5QV (SIRF) device. A framework for evaluating complex digital systems targeted for harsh radiation environments such as space is presented.
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A guideline for heavy ion radiation testing for single event upset was prepared to assist new experimenters in preparing and directing tests. How to estimate parts vulnerability and select an irradiation facility is described. A broad brush description of JPL equipment is given, certain necessary pre-test procedures are outlined and the roles and testing guidelines for on-site test personnel are indicated. Detailed descriptions of equipment needed to interface with JPL test crew and equipment are not provided, nor does it meet the more generalized and broader requirements of a MIL-STD document. A detailed equipment description is available upon request, and a MIL-STD document is in the early stages of preparation.
The data summarized describe single event upset (bit-flips) for 60 device types having data storage elements. The data are from 15 acceleration tests with both protons and heavier ions. Tables are included summarizing the upset threshold data and listing the devices tested for heavy ion induced bit-flip and the devices tested with protons. With regard to the proton data, it is noted that the data are often limited to one proton energy, since the tests were usually motivated by the engineering requirement of comparing similar candidate devices for a system. It is noted that many of the devices exhibited no upset for the given test conditions (the maximum fluence and the maximum proton energy Ep are given for these cases). It is believed, however, that some possibility of upset usually exists because there is a slight chance that the recoil atom may receive up to 10 to 20 MeV of recoil energy (with more energy at higher Ep).
A new logic family, which is immune to single event upsets, is described. Members of the logic family are capable of recovery, regardless of the shape of the upsetting event. Glitch propagation from an upset node is also blocked. Logic diagrams for an Inverter, Nor, Nand, and Complex Gates are provided. The logic family can be implemented in a standard, commercial CMOS process with no additional masks. DC, transient, static power, upset recovery and layout characteristics of the new family, based on a commercial 1 micron CMOS N-Well process, are described.
Fault testing of resistive manufacturing defects is done on a recently developed single event upset immune logic family. Resistive ranges and delay times are compared with those of traditional CMOS logic. Reaction of the logic to these defects is observed for a NOR gate, and an evaluation of its ability to cope with them is determined.
We now have considerable experience with successfully designing science systems to function properly, even during and after exposure to ionizing radiation approaching one Megarad, and during large solar particle events with substantial high Z fluxes such as the events that happened in August, 1972 and in the fall of 1989. Nevertheless, with changing device dimensions and properties, newer technologies and new applications, new problems arise. Some recent basic research has shed light on these problems and pointed the way to better diagnostic tests. In the case of single event upsets, clearly one cannot always accurately predict upset probabilities simply by knowing the quiescent Linear Energy Transfer (LET) threshold and the asymptotic cross-section of the device.