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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS1983

Production of large-area single-crystal wafers of cubic SiC for semiconductor devices

A reproducible process is described for growing a thick single-crystal layer of cubic SiC on a single-crystal Si wafer by chemical vapor deposition. A buffer layer, grown in situ, is used between the cubic SiC and the Si substrate to minimize the effect of lattice mismatch. Layers of up to 34 microns thick and several sq cm in area have been grown. Wafers are obtained by chemically removing the Si substrates from the grown layers. Excellent electron channeling patterns produced by these wafers indicate very good crystal quality. Preliminary electrical measurements have yielded electron mobilities up to 380 sq cm/Vs.

Nishino, S.↗
NASA NTRS1987

Wafer level reliability testing: An idea whose time has come

Wafer level reliability testing has been nurtured in the DARPA supported workshops, held each autumn since 1982. The seeds planted in 1982 have produced an active crop of very large scale integration manufacturers applying wafer level reliability test methods. Computer Aided Reliability (CAR) is a new seed being nurtured. Users are now being awakened by the huge economic value of the wafer reliability testing technology.

Trapp, O. D.↗
NASA NTRS1991

High temperature performance evaluation of a hypersonic engine ceramic wafer seal

Leakage rates of an innovative hypersonic engine seal were measured using a specially developed static high temperature seal test fixture at NASA Lewis Research Center. The three foot long structural panel-edge seal is designed to minimize leakage of high temperature, high pressure gases past the movable panels of advanced ramjet/scramjet engines. The seal is made of a stack of precision machined ceramic wafer pieces that are inserted into a closely conforming seal channel in the movable engine panel. The wafer seal accommodates the significant distortions in the adjacent engine walls through relative sliding between adjacent wafers. Seal leakage rates are presented for engine simulated air temperatures up to 1350 F and for engine pressures up to 100 psi. Leakage rates are also presented for the seal, sealing both a flat wall condition, and an engine simulated distorted wall condition in which the distortion was 0.15 in. in only an 18 in. span. Seal leakage rates were low, meeting an industry-established tentative leakage limit for all combinations of temperature, pressure, and wall conditions considered. Comparisons are made between the measured leakage rates and leakage rates predicted using a seal leakage model developed from externally-pressurized gas film bearing theory.

Steinetz, Bruce M.↗
NASA NTRS1991

Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

This invention is a method for the controlled growth of single-crystal semiconductor device quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

Powell, J. Anthony↗
NASA NTRS1995

Characterizing SOI Wafers By Use Of AOTF-PHI

Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

Cheng, Li-Jen↗
NASA NTRS1999

Microwave Induced Direct Bonding of Single Crystal Silicon Wafers

We have heated polished doped single-crystal silicon wafers in a single mode microwave cavity to temperatures where surface to surface bonding occurred. The absorption of microwaves and heating of the wafers is attributed to the inclusion of n-type or p-type impurities into these substrates. A cylindrical cavity TM (sub 010) standing wave mode was used to irradiate samples of various geometry's at positions of high magnetic field. This process was conducted in vacuum to exclude plasma effects. This initial study suggests that the inclusion of impurities in single crystal silicon significantly improved its microwave absorption (loss factor) to a point where heating silicon wafers directly can be accomplished in minimal time. Bonding of these substrates, however, occurs only at points of intimate surface to surface contact. The inclusion of a thin metallic layer on the surfaces enhances the bonding process.

Budraa, N. K.↗
NASA NTRS1999

On-Wafer Testing of Circuits Through 220 GHz

We have jointly developed the capability to perform on-wafer s-parameter and noise figure measurements through 220 GHz. S-parameter test sets have been developed covering full waveguide bands of 90-140 GHz (WR-08) and 140-220 GHz (WR-05). The test sets have been integrated with coplanar probes to allow accurate measurements on-wafer. We present the design and performance of the test sets and wafer probes. We also present calibration data as well as measurements of active circuits at frequencies as high as 215 GHz.

Gaier, Todd↗
NASA NTRS1997

W-Band On-Wafer Measurement of Uniplanar Slot-Type Antennas

Uniplanar slot-type antennas such as coplanar waveguide fed single- and dual-polarized slot-ring antennas and double folded-slot antennas are characterized using a millimeter-wave network analyzer and on-wafer measurement techniques. The antennas are designed to be mounted on a dielectric lens to minimize power loss into substrate modes and realize high-gain antenna patterns. On-wafer measurements are performed by placing the antenna wafer on a thick dielectric spacer of similar e(sub t) and eliminating the reflection from the probe station chuck with time-domain gating. The measured results agree well with method-of-moments simulations.

Raman, Sanjay↗
NASA NTRS2008

First On-Wafer Power Characterization of MMIC Amplifiers at Sub-Millimeter Wave Frequencies

Recent developments in semiconductor technology have enabled advanced submillimeter wave (300 GHz) transistors and circuits. These new high speed components have required new test methods to be developed for characterizing performance, and to provide data for device modeling to improve designs. Current efforts in progressing high frequency testing have resulted in on-wafer-parameter measurements up to approximately 340 GHz and swept frequency vector network analyzer waveguide measurements to 508 GHz. On-wafer noise figure measurements in the 270-340 GHz band have been demonstrated. In this letter we report on on-wafer power measurements at 330 GHz of a three stage amplifier that resulted in a maximum measured output power of 1.78mW and maximum gain of 7.1 dB. The method utilized demonstrates the extension of traditional power measurement techniques to submillimeter wave frequencies, and is suitable for automated testing without packaging for production screening of submillimeter wave circuits.

monolithic microwave integrated circircuit↗
NASA NTRS2018

NASA Feedback to DLA Land & Maritime Moratorium on Wafer Fab Audits

On September 29, 2017 the Defense Logistics Agency (DLA), Land and Maritime, announced that on September 1, 2017 they had begun a moratorium on the auditing of wafer fabrication facilities (fabs) used in the production of semiconductor die for military (MIL) qualified integrated circuits and discrete semiconductors (transistors and diodes). The announcement said the moratorium would last for six months initially and would apply to all wafer fabs qualified to MIL-PRF-19500 (discretes) and MIL-PRF-38535 (ICs) located, onshore or offshore. The stated rationale behind this action was to give DLA time to evaluate the risk of modifying current surveillance practices across 70+ Federal Stock Classes (FSC) under the jurisdiction of the DLA Qualifying Activity (VQ). The objective was to free up the resources used in these audits so they could be redirected towards audits of other commodities which were under resourced, notably connectors. In the announcement letter, DLA-VQ requested data from the community to assist with decisions on wafer fab re-audit cycle modifications. NASA used available information on current and historical audit schedules to gather such data and analyzed it to provide an in-depth understanding of the impact of locations, part types, in-house or out-of-house fabs on those schedules over time. This presentation provides the results of NASA's data analysis and suggest some changes to auditing practices that could increase efficient use of resources without significant increases in risk.

fab audits↗
NASA NTRS1967

Process controls introduction of selected impurities into semiconductor wafers

Modified three-step process controls the concentration of lithium diffused as a dopant into the base region of a diffused n-on-p silicon solar cell wafer. Part of the surface layer of the base region of the p-type silicon containing the diffused dopant is removed, prior to redistributing the remaining portion of the dopant into the bulk of the wafer.

Bartholomay, W. C.↗
NASA NTRS1968

Bonding large area silicon wafers

Diffusion welding of large area silicon wafers without altering electrical properties of semiconductor devices in wafers

Source record↗
NASA NTRS1969

Improved method of dicing integrated circuit wafers into chips

Method employing a pressure chamber is used for dicing semiconductor single-crystal wafers, containing integrated circuits, into small chips along pre-scribed lines. Uniform bending of the scribed wafer over the convex surface of a perforated hemisphere, breaks it cleanly into individual chips without damaging the circuits.

Litant, I.↗
NASA NTRS1975

Bubble-domain circuit wafer evaluation coil set

Coil structures have been designed to permit nondestructive testing of bubble wafers. Wafers can be electrically or optically inspected and operated from quasi-static frequency to maximum device operating frequency.

Chen, T. T.↗
NASA NTRS1978

Apparatus for use in examining the lattice of a semiconductor wafer by X-ray diffraction

An improved apparatus for examining the crystal lattice of a semiconductor wafer utilizing X-ray diffraction techniques was presented. The apparatus is employed in a method which includes the step of recording the image of a wafer supported in a bent configuration conforming to a compound curve, produced through the use of a vacuum chuck provided for an X-ray camera. The entire surface thereof is illuminated simultaneously by a beam of incident X-rays which are projected from a distant point-source and satisfy conditions of the Bragg Law for all points on the surface of the water.

Parker, D. L.↗
NASA NTRS1979

Remote manipulator for IC wafers

Mechanical manipulator automatically loads, transports, and unloads silicon wafers between processing stations in large-scale integrated-circuit fabrication facility at Marshall Space Flight Center thus eliminating need for human opeators at various stages in processing cycle. It also reduces possibility of wafer contamination.

Hudgins, J. L.↗
NASA NTRS1980

Automatic inspection of silicon wafers

Laser machine scans wafers for contaminating particles which cause open circuits, short circuits, and other defects in integrated circuits and transfers good wafers to integrated circuit processing equipment. Machine is faster and more accurate than human operator using lightfield/dark field microscope.

Martin, M.↗