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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
NASA NTRS1994

Transition From NASA Space Communication Systems to Commerical Communication Products

Transitioning from twenty-five years of space communication system architecting, engineering and development to creating and marketing of commercial communication system hardware and software products is no simple task for small, high-tech system engineering companies whose major source of revenue has been the U.S. Government. Yet, many small businesses are faced with this onerous and perplexing task. The purpose of this talk/paper is to present one small business (LinCom) approach to taking advantage of the systems engineering expertise and knowledge captured in physical neural networks and simulation software by supporting numerous National Aeronautics and Space Administration (NASA) and the Department of Defense (DoD) projects, e.g., Space Shuttle, TDRSS, Space Station, DCSC, Milstar, etc. The innovative ingredients needed for a systems house to transition to a wireless communication system products house that supports personal communication services and networks (PCS and PCN) development in a global economy will be discussed. Efficient methods for using past government sponsored space system research and development to transition to VLSI communication chip set products will be presented along with notions of how synergy between government and industry can be maintained to benefit both parties.

Ghazvinian, Farzad↗
NASA NTRS1993

Implementation and Performance of GaAs Digital Signal Processing ASICs

The feasibility of performing high speed digital signal processing in GaAs gate array technology has been demonstrated with the successful implementation of a VLSI communications chip set for NASA's Deep Space Network. This paper describes the techniques developed to solve some of the technology and implementation problems associated with large scale integration of GaAs gate arrays.

Whitaker, William D.↗
NASA NTRS2000

A Real-Time High Performance Data Compression Technique For Space Applications

A high performance lossy data compression technique is currently being developed for space science applications under the requirement of high-speed push-broom scanning. The technique is also error-resilient in that error propagation is contained within a few scan lines. The algorithm is based on block-transform combined with bit-plane encoding; this combination results in an embedded bit string with exactly the desirable compression rate. The lossy coder is described. The compression scheme performs well on a suite of test images typical of images from spacecraft instruments. Hardware implementations are in development; a functional chip set is expected by the end of 2001.

Yeh, Pen-Shu↗
NASA NTRS2010

Miniature MMIC Low Mass/Power Radiometer Modules for the 180 GHz GeoSTAR Array

We have developed and demonstrated miniature 180 GHz Monolithic Microwave Integrated Circuit (MMIC) radiometer modules that have low noise temperature, low mass and low power consumption. These modules will enable the Geostationary Synthetic Thinned Aperture Radiometer (GeoSTAR) of the Precipitation and All-weather Temperature and Humidity (PATH) Mission for atmospheric temperature and humidity profiling. The GeoSTAR instrument has an array of hundreds of receivers. Technology that was developed included Indium Phosphide (InP) MMIC Low Noise Amplifiers (LNAs) and second harmonic MMIC mixers and I-Q mixers, surface mount Multi-Chip Module (MCM) packages at 180 GHz, and interferometric array at 180 GHz. A complete MMIC chip set for the 180 GHz receiver modules (LNAs and I-Q Second harmonic mixer) was developed. The MMIC LNAs had more than 50% lower noise temperature (NT=300K) than previous state-of-art and MMIC I-Q mixers demonstrated low LO power (3 dBm). Two lots of MMIC wafers were processed with very high DC transconductance of up to 2800 mS/mm for the 35 nm gate length devices. Based on these MMICs a 180 GHz Multichip Module was developed that had a factor of 100 lower mass/volume (16x18x4.5 mm3, 3g) than previous generation 180 GHz receivers.

Monolithic Microwave Integrated Circuit (MMIC)↗
NASA NTRS2003

NASA Tech Briefs, December 2003

Topics covered include: Organic/Inorganic Hybrid Polymer/Clay Nanocomposites; Less-Toxic Coatings for Inhibiting Corrosion of Aluminum; Liquid Coatings for Reducing Corrosion of Steel in Concrete; Processable Polyimides Containing APB and Reactive End Caps; Rod/Coil Block Copolyimides for Ion-Conducting Membranes; Techniques for Characterizing Microwave Printed Antennas; Cylindrical Antenna With Partly Adaptive Phased-Array Feed; Command Interface ASIC - Analog Interface ASIC Chip Set; Predicting Accumulations of Ice on Aerodynamic Surfaces; Analyzing Aeroelasticity in Turbomachines; Software for Allocating Resources in the Deep Space Network; Expert Seeker; High-Speed Recording of Test Data on Hard Disks; Functionally Graded Nanophase Beryllium/Carbon Composites; Thin Thermal-Insulation Blankets for Very High Temperatures; Aerostructures Test Wing; Flight-Test Evaluation of Flutter-Prediction Methods; Piezoelectrically Actuated Microvalve for Liquid Effluents; Larger-Stroke Piezoelectrically Actuated Microvalve; Innovative, High-Pressure, Cryogenic Control Valve: Short Face-to-Face, Reduced Cost; Safer Roadside Crash Walls Would Limit Deceleration; Improved Interactive Medical-Imaging System; Scanning Microscopes Using X Rays and Microchannels; Slotting Fins of Heat Exchangers to Provide Thermal Breaks; Methane Clathrate Hydrate Prospecting; Automated Monitoring with a BSP Fault-Detection Test; Automated Monitoring with a BCP Fault-Decision Test; Vector-Ordering Filter Procedure for Data Reduction; Remote Sensing and Information Technology for Large Farms; Developments at the Advanced Design Technologies Testbed; Spore-Forming Bacteria that Resist Sterilization; and Acoustical Applications of the HHT Method.

Source record↗
NASA NTRS2013

Cosmo Cassette: A Microfluidic Microgravity Microbial System For Synthetic Biology Unit Tests and Satellite Missions

Although methods in the design-build-test life cycle of the synthetic biology field have grown rapidly, the expansion has been non-uniform. The design and build stages in development have seen innovations in the form of biological CAD and more efficient means for building DNA, RNA, and other biological constructs. The testing phase of the cycle remains in need of innovation. Presented will be both a theoretical abstraction of biological measurement and a practical demonstration of a microfluidics-based platform for characterizing synthetic biological phenomena. Such a platform demonstrates a design of additive manufacturing (3D printing) for construction of a microbial fuel cell (MFC) to be used in experiments carried out in space. First, the biocompatibility of the polypropylene chassis will be demonstrated. The novel MFCs will be cheaper, and faster to make and iterate through designs. The novel design will contain a manifold switchingdistribution system and an integrated in-chip set of reagent reservoirs fabricated via 3D printing. The automated nature of the 3D printing yields itself to higher resolution switching valves and leads to smaller sized payloads, lower cost, reduced power and a standardized platform for synthetic biology unit tests on Earth and in space. It will be demonstrated that the application of unit testing in synthetic biology will lead to the automatic construction and validation of desired constructs. Unit testing methodologies offer benefits of preemptive problem identification, change of facility, simplicity of integration, ease of documentation, and separation of interface from implementation, and automated design.

Bioelectrochemical System↗
NASA NTRS1995

The Clementine Mission

The Clementine Mission is summarized from purposes of the mission through details of the instruments. The mission was a joint Department of Defense and NASA mission to use lighter instruments and other equipment developed by the military for space exploration. New lightweight items on Clementine include batteries, optical sensors, reaction wheels, star trackers, release systems, and inertial measurement units. Other items include a compression chip set, a solid state data recorder, autonomous navigation, and a 32-bit RISC computer.

space↗
NASA NTRS1989

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

Buehler, M. G.↗
DOE OSTI2020

Setting operating points for circuits in an integrated circuit chip using an integrated voltage regulator power loss model

An apparatus includes an integrated circuit chip with a set of circuits having two or more subsets of circuits; an external voltage regulator separate from the integrated circuit chip; two or more integrated voltage regulators on the integrated circuit chip that each provide an input voltage to a respective subset of the circuits; and a controller. The controller determines, using an integrated voltage regulator power loss model, an electrical power loss for the integrated voltage regulators for a first combination of operating points for the subsets of the circuits. The controller then determines, based on the electrical power loss, a second combination of operating points for the subsets of the circuits that includes an adjustment to an operating point for at least one of the subsets of the circuits that compensates for an electrical power loss of the corresponding integrated voltage regulator. The controller sets an operating point of each of the subsets of the circuits based on the second combination of operating points.

42 ENGINEERING↗
NASA NTRS1991

Modular VLSI Reed-Solomon Decoder

Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.

Hsu, In-Shek↗
NASA NTRS1980

Azimuth correlator design for IC chip

Azimuth correlator circuit synthetic-aperature radar (SAR) is designed for single integrated circuit (IC) chip. Azimuth correlator modules constructed with sets of such chips could make real-time signal processing possible. Primary advantages are realized in areas of weight and power requirement reductions.

Tyree, V. C.↗
NASA NTRS2012

Wide Range SET Pulse Measurement

A method for measuring a wide range of SET pulses is demonstrated. Use of dynamic logic, faster than ordinary CMOS, allows capture of short pulses. A weighted binning of SET lengths allows measurement of a wide range of pulse lengths with compact circuitry. A pulse-length-conservative pulse combiner tree routes SETs from combinational logic to the measurement circuit, allowing SET measurements in circuits that cannot easily be arranged in long chains. The method is applied to add-multiplex combinational logic, and to an array of NFET routing switches, at .35 micron. Pulses are captured in a chain of Domino Logic AND gates. Propagation through the chain is frozen on the trailing edge by dropping low the second "enable" input to the AND gates. Capacitive loading is increased in the latter stages to create an approximately logarithmic weighted binning, so that a broad range of pulse lengths can be captured with a 10 stage capture chain. Simulations show pulses can be captured which are 1/5th the length of those typically captured with leading edge triggered latch methods, and less than the length of those captured with a trailing edge latch method. After capture, the pulse pattern is transferred to an SEU protected shift register for readout. 64 instances of each of two types of logic are used as targets. One is a full adder with a 4 to 1 mux on its inputs. The other is a 4 x 4 NFET routing matrix. The outputs are passed through buffered XNOR comparators to identify pulses, which are merged in a buffered not-nand (OR) tree designed to avoid pulse absorption as much as possible. The output from each of the two test circuits are input into separate pulse measurement circuits. Test inputs were provided so that the circuit could be bench tested and calibrated. A third SET measurement circuit with no inputs was used to judge the contribution from direct hits on the measurement circuit. Heavy ions were used with an LET range from 12 to 176. At LET of 21 and below, the very small number of SETs were not significantly higher in the test over the control circuits. At higher LET the test circuit SETs are one or two orders of magnitude greater than for the control circuit. The NFET circuit produces more and slightly longer SETs as expected. But the differences do not appear to be significant enough to modify strategies now used to avoid capture of SETs in chips such as FPGAs. Complete data and graphs will be in the full paper / presentation. In the summary figure below left, NOCL is the reference circuit without any input, and number of stages triggered is plotted. Simulation at right shows the smallest pulse captured (stage 2) at about 300 ps. Our conclusion is that the method is promising, but that improvements in the merge network are desirable before applying in a deep submicron process

Shuler, Robert L.↗
NASA NTRS1987

VLSI-Chip Tester

Compact test set integrated in computer-aided design system. Test set performs functional tests on very-large-scale integrated (VLSI) circuits. Makes tests from points within VLSI chip as well as at input and output pins. Used for quality control and design; in latter capacity, checks internal logic functions on chip and feed results directly to computer-aided design system for correction. Also simulates operation of chip design before chip is made. VLSI Tester contains three power supplies, control logic, and standard multibus circuit board in aluminum chassis. Chassis fits under platform of microprobe station. Multibus board links tester to interactive terminals and to host computer.

Deutsch, Leslie J.↗
NASA NTRS2007

Morphological Feature Extraction for Automatic Registration of Multispectral Images

The task of image registration can be divided into two major components, i.e., the extraction of control points or features from images, and the search among the extracted features for the matching pairs that represent the same feature in the images to be matched. Manual extraction of control features can be subjective and extremely time consuming, and often results in few usable points. On the other hand, automated feature extraction allows using invariant target features such as edges, corners, and line intersections as relevant landmarks for registration purposes. In this paper, we present an extension of a recently developed morphological approach for automatic extraction of landmark chips and corresponding windows in a fully unsupervised manner for the registration of multispectral images. Once a set of chip-window pairs is obtained, a (hierarchical) robust feature matching procedure, based on a multiresolution overcomplete wavelet decomposition scheme, is used for registration purposes. The proposed method is validated on a pair of remotely sensed scenes acquired by the Advanced Land Imager (ALI) multispectral instrument and the Hyperion hyperspectral instrument aboard NASA's Earth Observing-1 satellite.

Plaza, Antonio↗
NASA NTRS1995

Advanced packaging for Integrated Micro-Instruments

The relationship between packaging, microelectronics, and micro-electrical-mechanical systems (MEMS) is an important one, particularly when the edges of performance boundaries are pressed, as in the case of miniaturized systems. Packaging is a sort of physical backbone that enables the maximum performance of these systems to be realized, and the penalties imposed by conventional packing approaches is particularly limiting for MEMS devices. As such, advanced packaging approaches, such as multi-chip modules (MCM's) have been touted as a true means of electronic 'enablement' for a variety of application domains. Realizing an optimum system of packaging, however, in not as simple as replacing a set of single chip packages with a substrate of interconnections. Research at Phillips Laboratory has turned up a number of integrating options in the two- and three-dimensional rending of miniature systems with physical interconnection structures with intrinsically high performance. Not only do these structures motivate the redesign of integrated circuits (IC's) for lower power, but they possess interesting features that provide a framework for the direct integration of MEMS devices. Cost remains a barrier to the application of MEMS devices, even in space systems. Several innovations are suggested that will result in lower cost and more rapid cycle time. First, the novelty of a 'constant floor plan' MCM which encapsulates a variety of commonly used components into a stockable, easily customized assembly is discussed. Next, the use of low-cost substrates is examined. The anticipated advent of ultra-high density interconnect (UHDI) is suggested as the limit argument of advanced packaging. Finally, the concept of a heterogeneous 3-D MCM system is outlined that allows for the combination of different compatible packaging approaches into a uniformly dense structure that could also include MEMS-based sensors.

Lyke, James L.↗
NASA NTRS1981

Test of charge injection device, phase 1

A computer-controlled automatic facility containing two interactive microprocessors, peripherals, and an optical bench was used to obtain device characteristics for use in evaluating CID's as the sensor element in a prospective star tracker application. Each of the ST-256 chips tested contains a 256 x 256 pixel element array with 65536 picture elements. Two ST-256 devices were tested at 20 C under light levels of 10%, 0.1%, and 0.01% saturation, and in darkness. The saturation level was established at 0.95 microwatts sq cm as measured by the radiometeric sensor. Two test runs under each condition were performed for each chip. Two complete sets of data for each of the devices were thus obtained. A separate data field was used to store the results of each test condition. Repetitive runs of a test condition were stored sequentially in the same file. Examination of the data using print-outs is shown in examples.

Gradinger, A.↗
NASA NTRS1993

Rutger's CAM2000 chip architecture

This report describes the architecture and instruction set of the Rutgers CAM2000 memory chip. The CAM2000 combines features of Associative Processing (AP), Content Addressable Memory (CAM), and Dynamic Random Access Memory (DRAM) in a single chip package that is not only DRAM compatible but capable of applying simple massively parallel operations to memory. This document reflects the current status of the CAM2000 architecture and is continually updated to reflect the current state of the architecture and instruction set.

Smith, Donald E.↗