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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS1986

1986 Annual Conference on Nuclear and Space Radiation Effects, 23rd, Providence, RI, July 21-23, 1986, Proceedings

The present conference on the effects of nuclear and space radiation on electronic hardware gives attention to topics in the basic mechanisms of radiation effects, dosimetry and energy-dependent effects, electronic device radiation hardness assurance, SOI/SOS radiation effects, spacecraft charging and space radiation, IC radiation effects and hardening, single-event upset (SEU) phenomena and hardening, and EMP/SGEMP/IEMP phenomena. Specific treatments encompass the generation of interface states by ionizing radiation in very thin MOS oxides, the microdosimetry of meson energy deposited on 1-micron sites in Si, total dose radiation and engineering studies, plasma interactions with biased concentrator solar cells, the transient imprint memory effect in MOS memories, mechanisms leading to SEU, and the vaporization and breakdown of thin columns of water.

Ellis, Thomas D.↗
NASA NTRS1987

Response of a metal-oxide-semiconductor field-effect transistor to a cosmic-ray ion track

A cosmic-ray ion track passing perpendicularly through the oxide layer of an enhancement-mode metal-oxide-semiconductor field-effect transistor (MOSFET) forms a conducting path, the resistance of which is proportional to the stopping power of the cosmic ion and independent of the cross-sectional area of the ion track. The voltage across the oxide capacitance may drop below the threshold voltage if the gate bias is sufficiently low or if the external resistance in the gate-source circuit is sufficiently high. The first of a pair of MOSFETs forming a flip-flop circuit may thus be turned off, and the second transitor may turn on, providing it has a sufficiently short delay time, thereby completing a single-event upset.

Benumof, Reuben↗
NASA NTRS1988

Studies Of Single-Event-Upset Models

Report presents latest in series of investigations of "soft" bit errors known as single-event upsets (SEU). In this investigation, SEU response of low-power, Schottky-diode-clamped, transistor/transistor-logic (TTL) static random-access memory (RAM) observed during irradiation by Br and O ions in ranges of 100 to 240 and 20 to 100 MeV, respectively. Experimental data complete verification of computer model used to simulate SEU in this circuit.

Zoutendyk, J. A.↗
NASA NTRS1988

Refined Transistor Model For Simulation Of SEU

Equivalent base resistance added. Theoretical study develops equations for parameters of Gummel-Poon model of bipolar junction transistor: includes saturation current, amplification factors, charging times, knee currents, capacitances, and resistances. Portion of study concerned with base region goes beyond Gummel-Poon analysis to provide more complete understanding of transistor behavior. Extended theory useful in simulation of single-event upset (SEU) caused in logic circuits by cosmic rays or other ionizing radiation.

Zoutendyk, John A.↗
NASA NTRS1988

Self-Testing Computer Memory

Memory system for computer repeatedly tests itself during brief, regular interruptions of normal processing of data. Detects and corrects transient faults as single-event upsets (changes in bits due to ionizing radiation) within milliseconds after occuring. Self-testing concept surpasses conventional by actively flushing latent defects out of memory and attempting to correct before accumulating beyond capacity for self-correction or detection. Cost of improvement modest increase in complexity of circuitry and operating time.

Chau, Savio, N.↗
NASA NTRS1986

The Galileo Attitude and Articulation Control System - A radiation-hard, high precision, state-of-the-art control system

The Galileo Mission and Spacecraft design impose tight requirements on the Attitude and Articulation Control System (AACS). These requirements, coupled with the flexible spacecraft, the need for autonomy, and a severe radiation environment, pose a great challenge for the AACS designer. The resulting design and implementation are described, along with the discovery and solution of the Single-Event Upset problem. The status of the testing of the AACS in the Integration and Test Laboratory as well as at the spacecraft level is summarized.

Rhoads Stephenson, R.↗
NASA NTRS1987

1987 Annual Conference on Nuclear and Space Radiation Effects, Snowmass Village, CO, July 28-31, 1987, Proceedings

Various papers on nuclear and space radiation effects are presented. The general topics addressed include: basic mechanisms of radiation effects, single-event phenomena, temperature and field effects, modeling and characterization of radiation effects, IC radiation effects and hardening, and EMP/SGEMP/IEMP phenomena. Also considered are: dosimetry/energy-dependent effects, sensors in and for radiation environments, spacecraft charging and space radiation effects, radiation effects and devices, radiation effects on isolation technologies, and hardness assurance and testing techniques.

Source record↗
NASA NTRS1987

Quantification of the memory imprint effect for a charged particle environment

The effects of total accumulated dose on the single-event vulnerability of NMOS resistive-load SRAMs are investigated. The bias-dependent shifts in device parameters can imprint the memory state present during exposure or erase the imprinted state. Analysis of these effects is presented along with an analytic model developed for the quantification of these effects. The results indicate that the imprint effect is dominated by the difference in the threshold voltage of the n-channel devices.

Bhuva, B. L.↗
NASA NTRS1989

Spread Of Charge From Ion Tracks In Integrated Circuits

Single-event upsets (SEU's) propagate to adjacent cells in integrated memory circuits. Findings of experiments in lateral transport of electrical-charge carriers from ion tracks in 256K dynamic randon-access memories (DRAM's). As dimensions of integrated circuits decrease, vulnerability to SEU's increases. Understanding gained enables design of less vulnerable circuits.

Zoutendyk, John A.↗
NASA NTRS1989

SEU In An Advanced Bipolar Integrated Circuit

Report summarizes investigation of single-event upsets (SEU) in bipolar integrated-circuit set of flip-flops (memory cells). Device tested made by advanced digital bipolar silicon process of Honeywell, Inc. Circuit chip contained 4 cells. Construction enabled study of effect of size on SEU behavior. Each cell externally biased so effect of bias current on SEU behavior. Results of study provides important information for optimal design of devices fabricated using buried-layer bipolar process operating in heavy-ion SEU environments. Designers use information to provide required levels of suppression of SEU in specific applications via combinations of size and/or cell-current scaling.

Zoutendyk, John A.↗
NASA NTRS1989

Internal Correction Of Errors In A DRAM

Error-correcting Hamming code built into circuit. A 256 K dynamic random-access memory (DRAM) circuit incorporates Hamming error-correcting code in its layout. Feature provides faster detection and correction of errors at less cost in amount of equipment, operating time, and software. On-chip error-correcting feature also makes new DRAM less susceptible to single-event upsets.

Zoutendyk, John A.↗
NASA NTRS1988

Interplanetary Particle Environment. Proceedings of a Conference

A workshop entitled the Interplanetary Charged Particle Environment was held at the Jet Propulsion Laboratory (JPL) on March 16 and 17, 1987. The purpose of the Workshop was to define the environment that will be seen by spacecraft operating in the 1990s. It focused on those particles that are involved in single event upset, latch-up, total dose and displacement damage in spacecraft microelectronic parts. Several problems specific to Magellan were also discussed because of the sensitivity of some electronic parts to single-event phenomena. Scientists and engineers representing over a dozen institutions took part in the meeting. The workshop consisted of two major activities, reviews of the current state of knowledge and the formation of working groups and the drafting of their reports.

Feynman, Joan↗
NASA NTRS1988

1988 IEEE Annual Conference on Nuclear and Space Radiation Effects, 25th, Portland, OR, July 12-15, 1988, Proceedings

The effects of nuclear and space radiation on the performance of electronic devices are discussed in reviews and reports of recent investigations. Topics addressed include the basic mechanisms of radiation effects, dosimetry and energy-dependent effects, sensors in and for radiation environments, EMP/SGEMP/IEMP phenomena, radiation effects on isolation technologies, and spacecraft charging and space radiation effects. Consideration is given to device radiation effects and hardening, hardness assurance and testing techniques, IC radiation effects and hardening, and single-event phenomena.

Coakley, Peter G.↗
NASA NTRS1988

Full temperature single event upset characterization of two microprocessor technologies

Data for the 9450 I3L bipolar microprocessor and the 80C86 CMOS/epi (vintage 1985) microprocessor are presented, showing single-event soft errors for the full MIL-SPEC temperature range of -55 to 125 C. These data show for the first time that the soft-error cross sections continue to decrease with decreasing temperature at subzero temperatures. The temperature dependence of the two parts, however, is very different.

Nichols, Donald K.↗
NASA NTRS1990

Asymmetric Memory Circuit Would Resist Soft Errors

Some nonlinear error-correcting codes more efficient in presence of asymmetry. Combination of circuit-design and coding concepts expected to make integrated-circuit random-access memories more resistant to "soft" errors (temporary bit errors, also called "single-event upsets" due to ionizing radiation). Integrated circuit of new type made deliberately more susceptible to one kind of bit error than to other, and associated error-correcting code adapted to exploit this asymmetry in error probabilities.

Buehler, Martin G.↗
NASA NTRS1990

Upper-Bound Estimates Of SEU in CMOS

Theory of single-event upsets (SEU) (changes in logic state caused by energetic charged subatomic particles) in complementary metal oxide/semiconductor (CMOS) logic devices extended to provide upper-bound estimates of rates of SEU when limited experimental information available and configuration and dimensions of SEU-sensitive regions of devices unknown. Based partly on chord-length-distribution method.

Edmonds, Larry D.↗
NASA NTRS1990

Exact Chord-Length Distribution For SEU Calculations

Computed rates of SEU's more accurate. Exact integral chord-length distribution derived for use in calculations of rates of single-event upsets (SEU's) (changes in logic states) caused by impingement of cosmic rays or other ionizing radiation on electronic logic circuits.

Buehler, Martin G.↗
NASA NTRS1989

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

Buehler, M. G.↗