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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 559 records · Page 31
All sourcesNASA NTRSDOE OSTI
NASA NTRS2008

Efficient G(sup 4)FET-Based Logic Circuits

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

Vatan, Farrokh↗
DOE OSTI2024

Construction of Reconfigurable and Polymorphic DNA Origami Assemblies with Coiled‐Coil Patches and Patterns

Abstract DNA origami nanodevices achieve programmable structure and tunable mechanical and dynamic properties by leveraging the sequence‐specific interactions of nucleic acids. Previous advances have also established DNA origami as a useful building block to make well‐defined micron‐scale structures through hierarchical self‐assembly, but these efforts have largely leveraged the structural features of DNA origami. The tunable dynamic and mechanical properties also provide an opportunity to make assemblies with adaptive structures and properties. Here the integration of DNA origami hinge nanodevices and coiled‐coil peptides are reported into hybrid reconfigurable assemblies. With the same dynamic device and peptide interaction, it is made multiple higher‐order assemblies (i.e., polymorphic assembly) by organizing clusters of peptides into patches or arranging single peptides into patterns on the surfaces of DNA origami to control the relative orientation of devices. The coiled‐coil interactions are used to construct circular and linear assemblies whose structure and mechanical properties can be modulated with DNA‐based reconfiguration. Reconfiguration of linear assemblies leads to micron scale motions and ≈2.5‐10‐fold increase in bending stiffness. The results provide a foundation for stimulus‐responsive hybrid assemblies that can adapt their structure and properties in response to nucleic acid, peptide, protein, or other triggers.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2017

Benchmarking and Evaluating Unified Memory for OpenMP GPU Offloading

Here, the latest OpenMP standard offers automatic device offloading capabilities which facilitate GPU programming. Despite this, there remain many challenges. One of these is the unified memory feature introduced in recent GPUs. GPUs in current and future HPC systems have enhanced support for unified memory space. In such systems, CPU and GPU can access each other's memory transparently, that is, the data movement is managed automatically by the underlying system software and hardware. Memory over subscription is also possible in these systems. However, there is a significant lack of knowledge about how this mechanism will perform, and how programmers should use it. We have modified several benchmarks codes, in the Rodinia benchmark suite, to study the behavior of OpenMP accelerator extensions and have used them to explore the impact of unified memory in an OpenMP context. We moreover modified the open source LLVM compiler to allow OpenMP programs to exploit unified memory. The results of our evaluation reveal that, while the performance of unified memory is comparable with that of normal GPU offloading for benchmarks with little data reuse, it suffers from significant overhead when GPU memory is over subcribed for benchmarks with large amount of data reuse. Based on these results, we provide several guidelines for programmers to achieve better performance with unified memory.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

Toward Evaluating High-Level Synthesis Portability and Performance between Intel and Xilinx FPGAs

Offloading computation from a CPU to a hardware accelerator is becoming a more common solution for improving performance because traditional gains enabled by Moore’s law and Dennard scaling have slowed. GPUs are often used as hardware accelerators, but field-programmable gate arrays (FPGAs) are gaining traction. FPGAs are beneficial because they allow hardware specific to a particular application to be created. However, they are notoriously difficult to program. To this end, two of the main FPGA manufacturers, Intel and Xilinx, have created tools and frameworks that enable the use of higher level languages to design FPGA hardware. Although Xilinx kernels can be designed by using C/C++, both Intel and Xilinx support the use of OpenCL C to architect FPGA hardware. However, not much is known about the portability and performance between these two device families other than the fact that it is theoretically possible to synthesize a kernel meant for Intel to Xilinx and vice versa.In this work, we evaluate the portability and performance of Intel and Xilinx kernels. We use OpenCL C implementations of a subset of the Rodinia benchmarking suite that were designed for an Intel FPGA and make the necessary modifications to create synthesizable OpenCL C kernels for a Xilinx FPGA. We find that the difficulty of porting certain kernel optimizations varies, depending on the construct. Once the minimum amount of modifications is made to create synthesizable hardware for the Xilinx platform, more nontrivial work is needed to improve performance. However, we find that constructs that are known to be performant for an FPGA should improve performance regardless of the platform; the difficulty comes in deciding how to invoke certain kernel optimizations while also abiding by the constraints enforced by a given platform’s hardware compiler.

Cabrera, Anthony↗
NASA NTRS1999

Advanced Design and Implementation of a Control Architecture for Long Range Autonomous Planetary Rovers

An advanced design and implementation of a Control Architecture for Long Range Autonomous Planetary Rovers is presented using a hierarchical top-down task decomposition, and the common structure of each design is presented based on feedback control theory. Graphical programming is presented as a common intuitive language for the design when a large design team is composed of managers, architecture designers, engineers, programmers, and maintenance personnel. The whole design of the control architecture consists in the classic control concepts of cyclic data processing and event-driven reaction to achieve all the reasoning and behaviors needed. For this purpose, a commercial graphical tool is presented that includes the mentioned control capabilities. Messages queues are used for inter-communication among control functions, allowing Artificial Intelligence (AI) reasoning techniques based on queue manipulation. Experimental results show a highly autonomous control system running in real time on top the JPL micro-rover Rocky 7 controlling simultaneously several robotic devices. This paper validates the sinergy between Artificial Intelligence and classic control concepts in having in advanced Control Architecture for Long Range Autonomous Planetary Rovers.

Martin-Alvarez, A.↗
NASA NTRS2003

ASRC Aerospace Corporation Selects Dynamically Reconfigurable Anadigm(Registered Trademark) FPAA For Advanced Data Acquisition System

Anadigm(registered trademark) today announced that ASRC Aerospace Corporation has designed Anadigm's dynamically reconfigurable Field Programmable Analog Array (FPAA) technology into an advanced data acquisition system developed under contract for NASA. ASRC Aerospace designed in the Anadigm(registered trademark) FPAA to provide complex analog signal conditioning in its intelligent, self-calibrating, and self-healing advanced data acquisition system (ADAS). The ADAS has potential applications in industrial, manufacturing, and aerospace markets. This system offers highly reliable operation while reducing the need for user interaction. Anadigm(registered trademark)'s dynamically reconfigurable FPAAs can be reconfigured in-system by the designer or on the fly by a microprocessor. A single device can thus be programmed to implement multiple analog functions and/or to adapt on-the-fly to maintain precision operation despite system degradation and aging. In the case of the ASRC advanced data acquisition system, the FPAA helps ensure that the system will continue to operating at 100% functionality despite changes in the environment, component degradation, and/or component failures.

Mata, Carlos T.↗
NASA NTRS2015

Single Event Effects in FPGA Devices 2014-2015

This presentation provides an overview of single event effects in FPGA devices 2014-2015 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing. Mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.

Single event upset (SEU)↗
DOE OSTI2024

HDBind: encoding of molecular structure with hyperdimensional binary representations

Traditional methods for identifying “hit” molecules from a large collection of potential drug-like candidates rely on biophysical theory to compute approximations to the Gibbs free energy of the binding interaction between the drug and its protein target. These approaches have a significant limitation in that they require exceptional computing capabilities for even relatively small collections of molecules. Increasingly large and complex state-of-the-art deep learning approaches have gained popularity with the promise to improve the productivity of drug design, notorious for its numerous failures. However, as deep learning models increase in their size and complexity, their acceleration at the hardware level becomes more challenging. Hyperdimensional Computing (HDC) has recently gained attention in the computer hardware community due to its algorithmic simplicity relative to deep learning approaches. The HDC learning paradigm, which represents data with high-dimension binary vectors, allows the use of low-precision binary vector arithmetic to create models of the data that can be learned without the need for the gradient-based optimization required in many conventional machine learning and deep learning methods. This algorithmic simplicity allows for acceleration in hardware that has been previously demonstrated in a range of application areas (computer vision, bioinformatics, mass spectrometery, remote sensing, edge devices, etc.). To the best of our knowledge, our work is the first to consider HDC for the task of fast and efficient screening of modern drug-like compound libraries. We also propose the first HDC graph-based encoding methods for molecular data, demonstrating consistent and substantial improvement over previous work. We compare our approaches to alternative approaches on the well-studied MoleculeNet dataset and the recently proposed LIT-PCBA dataset derived from high quality PubChem assays. We demonstrate our methods on multiple target hardware platforms, including Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs), showing at least an order of magnitude improvement in energy efficiency versus even our smallest neural network baseline model with a single hidden layer. Our work thus motivates further investigation into molecular representation learning to develop ultra-efficient pre-screening tools. We make our code publicly available at https://github.com/LLNL/hdbind.

59 BASIC BIOLOGICAL SCIENCES↗
NASA NTRS2016

Single Event Effects in FPGA Devices 2015-2016

This presentation provides an overview of single event effects in FPGA devices 2015-2016 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing. Mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.

Single Event Upset (SEU) Testing↗
DOE OSTI2024

Nanoscale Ferroelectric Programming of van der Waals Heterostructures

We demonstrate an approach to creating nanoscale potentials in van der Waals layers integrated with a buried programmable ferroelectric layer. Using ultra-low-voltage electron beam lithography (ULV-EBL), we can program the ferroelectric polarization in Al 1–x B x N (AlBN) thin films, generating structures with sizes as small as 35 nm. We demonstrate the ferroelectric field effect with a graphene/vdW stack on AlBN by creating a p–n junction. This resist-free, high-resolution, contactless patterning method offers a new pathway to integrate ferroelectric films with a wide range of two-dimensional layers including transition-metal dichalcogenides (TMD), enabling arbitrary programming and top-down creation of multifunctional devices.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2024

Strain-concentration for fast, compact photonic modulation and non-volatile memory

A critical figure of merit (FoM) for electro-optic (EO) modulators is the transmission change per voltage, d T / d V . Conventional approaches in wave-guided modulators maximize d T / d V via a high EO coefficient or longer light-material interaction lengths but are ultimately limited by material losses and nonlinearities. Optical and RF resonances improve d T / d V at the cost of spectral non-uniformity, especially for high- Q optical cavity resonances. Here, we introduce an EO modulator based on piezo-strain-concentration of a photonic crystal cavity to address both trade-offs: (i) it eliminates the trade-off between d T / d V and waveguide loss—i.e., enhancement of the resonance tuning efficiency d v c / d V for the fixed EO coefficient, waveguide length, and cavity Q —and (ii) at high DC strains it exhibits a non-volatile (NV) cavity tuning Δ v c ,NV for passive memory and programming of multiple devices into resonance despite fabrication variations. The device is fabricated on a scalable silicon nitride-on-aluminum nitride platform. We measure d v c / d V =177±1MHz/V, corresponding to Δ v c =40±0.32GHz for a voltage spanning ±120V with an energy consumption of δ U /Δ v c =0.17nW/GHz. The modulation bandwidth is flat up to ω BW,3dB /2 π =3.2±0.07MHz for broadband DC-AC and 142±17MHz for resonant operation near a 2.8 GHz mechanical resonance. Optical extinction up to 25 dB is obtained via Fano-type interference. Strain-induced beam-buckling modes are programmable under a “read-write” protocol with a continuous, repeatable tuning range of 5±0.25GHz, allowing for storage and retrieval, which we quantify with mutual information of 2.4 bits and a maximum non-volatile excursion of 8 GHz. Using a full piezo-optical finite-element-model (FEM) we identify key design principles for optimizing strain-based modulators and chart a path towards achieving performance comparable to lithium niobate-based modulators and the study of high strain physics on-chip.

Wen, Y. Henry (ORCID:0009000685423628)↗
DOE OSTI2024

Entropy Analysis of FPGA Interconnect and Switch Matrices for Physical Unclonable Functions

Random variations in microelectronic circuit structures represent the source of entropy for physical unclonable functions (PUFs). In this paper, we investigate delay variations that occur through the routing network and switch matrices of a field-programmable gate array (FPGA). The delay variations are isolated from other components of the programmable logic, e.g., look-up tables (LUTs), flip-flops (FFs), etc., using a feature of Xilinx FPGAs called dynamic partial reconfiguration (DPR). A set of partial designs is created to fix the placement of a time-to-digital converter (TDC) and supporting infrastructure to enable the path delays through the target interconnect and switch matrices to be extracted by subtracting out common-mode delay components. Delay variations are analyzed in the different levels of routing resources available within FPGAs, i.e., local routing and across-chip routing. Data are collected from a set of Xilinx Zynq 7010 devices, and a statistical analysis of within-die variations in delay through a set of the randomly-generated and hand-crafted interconnects is presented.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS2002

Novel Advancements in Internet-Based Real Time Data Technologies

AZ Technology has been working with MSFC Ground Systems Department to find ways to make it easier for remote experimenters (RPI's) to monitor their International Space Station (ISS) payloads in real-time from anywhere using standard/familiar devices. AZ Technology was awarded an SBIR Phase I grant to research the technologies behind and advancements of distributing live ISS data across the Internet. That research resulted in a product called "EZStream" which is in use on several ISS-related projects. Although the initial implementation is geared toward ISS, the architecture and lessons learned are applicable to other space-related programs. This paper presents the high-level architecture and components that make up EZStream. A combination of commercial-off-the-shelf (COTS) and custom components were used and their interaction will be discussed. The server is powered by Apache's Jakarta-Tomcat web server/servlet engine. User accounts are maintained in a My SQL database. Both Tomcat and MySQL are Open Source products. When used for ISS, EZStream pulls the live data directly from NASA's Telescience Resource Kit (TReK) API. TReK parses the ISS data stream into individual measurement parameters and performs on-the- fly engineering unit conversion and range checking before passing the data to EZStream for distribution. TReK is provided by NASA at no charge to ISS experimenters. By using a combination of well established Open Source, NASA-supplied. and AZ Technology-developed components, operations using EZStream are robust and economical. Security over the Internet is a major concern on most space programs. This paper describes how EZStream provides for secure connection to and transmission of space- related data over the public Internet. Display pages that show sensitive data can be placed under access control by EZStream. Users are required to login before being allowed to pull up those web pages. To enhance security, the EZStream client/server data transmissions can be encrypted to preclude interception. EZStream was developed to make use of a host of standard platforms and protocols. Each are discussed in detail in this paper. The I3ZStream server is written as Java Servlets. This allows different platforms (i.e. Windows, Unix, Linux . Mac) to host the server portion. The EZStream client component is written in two different flavors: JavaBean and ActiveX. The JavaBean component is used to develop Java Applet displays. The ActiveX component is used for developing ActiveX-based displays. Remote user devices will be covered including web browsers on PC#s and scaled-down displays for PDA's and smart cell phones. As mentioned. the interaction between EZStream (web/data server) and TReK (data source) will be covered as related to ISS. EZStream is being enhanced to receive and parse binary data stream directly. This makes EZStream beneficial to both the ISS International Partners and non-NASA applications (i.e. factory floor monitoring). The options for developing client-side display web pages will be addressed along with the development of tools to allow creation of display web pages by non-programmers.

Myers, Gerry↗
NASA NTRS2009

XML Translator for Interface Descriptions

A computer program defines an XML schema for specifying the interface to a generic FPGA from the perspective of software that will interact with the device. This XML interface description is then translated into header files for C, Verilog, and VHDL. User interface definition input is checked via both the provided XML schema and the translator module to ensure consistency and accuracy. Currently, programming used on both sides of an interface is inconsistent. This makes it hard to find and fix errors. By using a common schema, both sides are forced to use the same structure by using the same framework and toolset. This makes for easy identification of problems, which leads to the ability to formulate a solution. The toolset contains constants that allow a programmer to use each register, and to access each field in the register. Once programming is complete, the translator is run as part of the make process, which ensures that whenever an interface is changed, all of the code that uses the header files describing it is recompiled.

Boroson, Elizabeth R.↗
DOE OSTI2025

Mesoporous Thin Film Architectures: Addressing Material Demands through Molecular Self-Assembly

Mesoporous thin films spark interest across a wide range of disciplines due to their tunable nanostructures, large internal surface areas, and strong compatibility with planar optical, electronic, and microfluidic devices. While attention in the porous materials community has shifted toward macroporous or disordered nanoporous systems, a resurgence in mesoporous thin film research is underway, driven by new molecular self-assembly methods, advanced materials chemistry, and improved characterization techniques. The integration of high-χN block copolymer design, kinetically persistent micelle templating, and postdeposition processing protocols now allows control over structural parameters such as pore size, wall thickness, porosity, and connectivity. These advances have overcome many of the thermodynamic and processing constraints that previously limited widespread adoption. Rather than serving only as high-surface-area supports, mesoporous thin films are engineered as active interfaces where responsive chemistries and nanoscale confinement act in tandem. Embedding switchable ligands, thermoresponsive polymers, redox mediators, or ion-selective groups directly within the pore walls enables real-time control over transport, optical, and electrochemical properties. These capabilities open up new directions in adaptive coatings, gated membranes, and fast-response biosensors. To further expand their functional scope, mesoporous films are integrated into hierarchical and multicomponent architectures. Techniques such as triblock terpolymer templating, crack-directed assembly, and nanoimprint lithography allow for control over spatial organization on the micron and submicron scale and pore system orientation. This enables programmable anisotropy, enhanced molecular diffusion, and wavelength-selective photonic behavior, essential for next-generation sensing, catalysis, and energy applications. Such structural and functional complexity requires equally sophisticated characterization. Multimodal and in situ techniques can track material dynamics under operational conditions. Recent progress includes extended-range ellipsometric porosimetry (EP) for hierarchical architectures, vacuum EP for interface energetics, time-resolved EP for diffusion kinetics, and correlative AFM-SAXS mapping. The introduction of advanced neutron-based spectroscopies, particularly quasielastic neutron scattering (QENS), promises to provide real-time access to ion transport dynamics and segmental motion under nanoscale confinement, offering a path toward deeper mechanistic understanding of structure-performance correlations in mesoporous systems. This Account reflects the technical advances made and the interdisciplinary collaborations that have shaped our collective vision. The particular dimensions of mesopores enable us to subtly tune interactions at the molecular, interfacial, and mesoscopic levels that permit us to harness nanoconfinement. What emerges is a versatile, modular platform capable of chemical gating, energy transduction, and sensing with a level of tunability unmatched by other porous materials. We highlight critical challenges including the need for more robust large-area processing, a deeper understanding of dynamic behavior under cycling, and better integration with device-level architectures. Our strategies support the transition of mesoporous thin films into active high-performance components in next-generation energy, environmental, and biomedical systems.

oxides↗
DOE OSTI2024

Overview of the EUROfusion Tokamak Exploitation programme in support of ITER and DEMO

Within the 9th European Framework programme, since 2021 EUROfusion is operating five tokamaks under the auspices of a single Task Force called ‘Tokamak Exploitation’. The goal is to benefit from the complementary capabilities of each machine in a coordinated way and help in developing a scientific output scalable to future largre machines. The programme of this Task Force ensures that ASDEX Upgrade, MAST-U, TCV, WEST and JET (since 2022) work together to achieve the objectives of Missions 1 and 2 of the EUROfusion Roadmap: i) demonstrate plasma scenarios that increase the success margin of ITER and satisfy the requirements of DEMO and, ii) demonstrate an integrated approach that can handle the large power leaving ITER and DEMO plasmas. The Tokamak Exploitation task force has therefore organized experiments on these two missions with the goal to strengthen the physics and operational basis for the ITER baseline scenario and for exploiting the recent plasma exhaust enhancements in all four devices (PEX: Plasma EXhaust) for exploring the solution for handling heat and particle exhaust in ITER and develop the conceptual solutions for DEMO. The ITER Baseline scenario has been developed in a similar way in ASDEX Upgrade, TCV and JET. Key risks for ITER such as disruptions and run-aways have been also investigated in TCV, ASDEX Upgrade and JET. Experiments have explored successfully different divertor configurations (standard, super-X, snowflakes) in MAST-U and TCV and studied tungsten melting in WEST and ASDEX Upgrade. The input from the smaller devices to JET has also been proven successful to set-up novel control schemes on disruption avoidance and detachment.

ASDEX upgrade↗
NASA NTRS2008

Contrast Measurements of the Microshutter Arrays for the NIRspec

We have been developing programmable microshutter arrays for the Near Infrared Spectrometer (NIRSpec) on the James Webb Space telescope (JWST). These arrays are an enabling technology that allows to turn NIRSpec into a powerful multi-object spectrometer and tremendously increase its efficiency. The arrays are essentially 2D programmable masks that are designed to operate at cryogenic temperatures of JWST. The primary optical characteristic of the microshutter array is a contrast, that is defined as a ratio of the transmitted light intensity through open shutters to the intensity of the transmitted light through the closed shutters. To eliminate the noise and confusion from other sources in the field of view and therefore to improve the detection limit, the contrast provided by the microshutter array should be very high, with the goal of 10,000. The test system that we have developed specifically for the purpose of the high contrast characterization of the microshutter array devices has been used to test several microshutter arrays. It is capable of measuring contrast values of up to 10^5 and therefore can reliably measure contrast values of the arrays that satisfy the requirements. The arrays have been characterized for the contrast ratio and its behavior with temperature and other array operating parameters. The arrays that we have tested meet or exceed the NiRSpec requirements.

Kutyrev, Alexander↗
NASA NTRS2009

Evaluation of a Programmable Voltage-Controlled MEMS Oscillator, Type SiT3701, Over a Wide Temperature Range

Semiconductor chips based on MEMS (Micro-Electro-Mechanical Systems) technology, such as sensors, transducers, and actuators, are becoming widely used in today s electronics due to their high performance, low power consumption, tolerance to shock and vibration, and immunity to electro-static discharge. In addition, the MEMS fabrication process allows for the miniaturization of individual chips as well as the integration of various electronic circuits into one module, such as system-on-a-chip. These measures would simplify overall system design, reduce parts count and interface, improve reliability, and reduce cost; and they would meet requirements of systems destined for use in space exploration missions. In this work, the performance of a recently-developed MEMS voltage-controlled oscillator was evaluated under a wide temperature range. Operation of this new commercial-off-the-shelf (COTS) device was also assessed under thermal cycling to address some operational conditions of the space environment

Patterson, Richard↗