An all monolithic MOS A/D converter - Low power clocks, multiplexers, registers, and A/D converter Final report
Research and developments of monolithic, MOS, ten bit, analog to digital converter
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Research and developments of monolithic, MOS, ten bit, analog to digital converter
Bipolar n-p-n transistors fabrication to increase driving capabilities of complementary MOS transistors while retaining low power dissipation
Design and performance of logic circuit chip for computerized design of MOS integrated circuit arrays
Possible electron irradiated failure modes of MOS micrometeoroid capacitor detectors
MOS capacitors as low mass micrometeoroid detectors in near-earth space, discussing fabrication and environmental tests
MOS transistors and bipolar microcircuits mobile charge density, observing p-n junction effects
Capacitance voltage measurements on interface of pyrolytically deposited n-type silicon dioxide- InAs MOS diodes as function of admittance at room and 77 K temperatures
Insulator surface ion migration effects on MOS and bipolar integrated circuits, describing inversion voltage and surface conductivity and recombination velocities
Beam-lead technology application to complementary MOS IC processing
Speed required for Sisyphus experiment on Pioneer probe was attained at supply voltage well within component limitations by combining supply voltage higher than nominal with low reactance interconnections. Speed was found to be far in excess of typical. parameters suggested by manufacturers of MOS devices.
An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. N-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on an oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift in C-V curve under 200 C plus or minus 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous.
Several circuits can be integrated into one chip for applications which require more than one gyrator. They can also be integrated with other p-channel MOS circuits to eliminate need for external connections. Devices can operate at economical low-power levels, because they use FET amplifiers that do not degrade with decreases in supply.
A shielded integrated complimentary MOS transistor structure is described which is used to prevent field inversion in the region not occupied by the gates and which permits the use of a thinner field oxide, reduces the chip area, and has provision for simplified multilayer connections. The structure is used in the design of a static shift register and results in a 20% reduction in area.
Recent results on tunneling in thin MOS structures are described. Thermally grown SiO2 films in the thickness range of 22-40 A have been shown to be effectively uniform on an atomic scale and exhibit an extremely abrupt oxide-silicon interface. Resonant reflections are observed at this interface for Fowler-Nordheim tunneling and are shown to agree with the exact theory for a trapezoidal barrier. Tunneling at lower fields is consistent with elastic tunneling into the silicon direct conduction band and, at still lower fields, inelastic tunneling into the indirect conduction band. Approximate dispersion relations are obtained over portions of the silicon-dioxide energy gap and conduction band.
Oscillatory deviations from Fowler-Nordheim tunneling currents were measured in MOS capacitors with oxide thicknesses ranging from 30 to 75 A. The observed variation of oscillation phases and amplitudes with oxide thickness indicates that the Si-SiO2 interface is independent of oxide thickness only for thicknesses greater than 65 A. At lower thicknesses, the barrier height at the interface decreases gradually with oxide thickness at a rate on the order of 10 mV/A. At higher thicknesses, the barrier height is 4.08 eV. The energy dispersion relation with the SiO2 conduction band is parabolic. The mean free path within the SiO2 conduction band is on the order of 13 A.
An experimental and theoretical investigation of the feasibility of using the MOS C-V (capacitance-voltage) technique to determine impurity and surface state concentrations on the diffused face of Si solar cells with Ta2O5 coatings. Impurity concentration 10 A from the diffused surface is found to be 2.9 times 10 to the 20th power per cu cm. Charge density in surface and oxide states is 2.1 times 10 to the 13th power per sq cm. These data agree with theoretical predictions.-
The statistical nature of time-dependent dielectric breakdown characteristics in MOS capacitors was evidenced by testing large numbers of capacitors fabricated on single wafers. A multipoint probe and automatic electronic visual display technique are introduced that will yield statistical results which are necessary for the investigation of temperature, electric field, thermal annealing, and radiation effects in the breakdown characteristics, and an interpretation of the physical mechanisms involved. It is shown that capacitors of area greater than 0.002 sq cm may yield worst-case results, and that a multipoint probe of capacitors of smaller sizes can be used to obtain a profile of nonuniformities in the SiO2 films.
A general model for time-dependent breakdown in metal-oxide-silicon (MOS) structures is developed and related to experimental measurements on samples deliberately contaminated with Na. A statistical method is used for measuring the breakdown probability as a function of log time and applied field. It is shown that three time regions of breakdown can be explained respectively in terms of silicon surface defects, ion emission from the metal interface, and lateral ion diffusion at the silicon interface.