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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
NASA NTRS2001

The gating mechanism of the large mechanosensitive channel MscL

The mechanosensitive channel of large conductance, MscL, is a ubiquitous membrane-embedded valve involved in turgor regulation in bacteria. The crystal structure of MscL from Mycobacterium tuberculosis provides a starting point for analysing molecular mechanisms of tension-dependent channel gating. Here we develop structural models in which a cytoplasmic gate is formed by a bundle of five amino-terminal helices (S1), previously unresolved in the crystal structure. When membrane tension is applied, the transmembrane barrel expands and pulls the gate apart through the S1-M1 linker. We tested these models by substituting cysteines for residues predicted to be near each other only in either the closed or open conformation. Our results demonstrate that S1 segments form the bundle when the channel is closed, and crosslinking between S1 segments prevents opening. S1 segments interact with M2 when the channel is open, and crosslinking of S1 to M2 impedes channel closing. Gating is affected by the length of the S1-M1 linker in a manner consistent with the model, revealing critical spatial relationships between the domains that transmit force from the lipid bilayer to the channel gate.

Non-NASA Center↗
DOE OSTI2024

Fast Z Z free entangling gates for superconducting qubits assisted by a driven resonator

Engineering high-fidelity two-qubit gates is an indispensable step toward practical quantum computing. For superconducting quantum platforms, one important setback is the stray interaction between qubits, which causes significant coherent errors. For transmon qubits, protocols for mitigating such errors usually involve fine-tuning the hardware parameters or introducing usually noisy flux-tunable couplers. In this work, we propose a simple scheme to cancel these stray interactions. The coupler used for such cancelation is a driven high-coherence resonator, where the amplitude and frequency of the drive serve as control knobs. Through the resonator-induced-phase interaction, the static Z Z coupling can be entirely neutralized. We numerically show that such a scheme can enable short and high-fidelity entangling gates, including cross-resonance controlled-not (cnot) gates within 40 ns and adiabatic controlled- Z gates within 140 ns. Our architecture is not only Z Z -free, but also contains no extra noisy components, such that it preserves the coherence times of fixed-frequency transmon qubits. With the state-of-the-art coherence times, the error of our cross-resonance cnot gate can be reduced to below 10 − 4 .

Huang, Ziwen↗
NASA NTRS1984

GaAs dual-gate FET for operation up to K-band

A high-frequency equivalent-circuit model of a GaAs dual-gate FET and analytical expressions for the input/output impedances, transconductance, unilateral gain, and stability factor are presented. It is found that the gain of a dual-gate FET is higher than of a single-gate FET at low frequency but decreases faster as frequency increases because of the capacitive shunting effect of the second gate. A dual-gate power FET suitable for variable-gain-amplifier applications up to K-band has been developed. At 10 GHz, a 1.2-mm-gatewidth device has achieved an output power of 1.1 W with 10.5-dB gain and 31-percent power-added efficiency. At 20 GHz, the same device delivered an output power of 340 mW with 5.3-dB gain. At K-band, a dynamic-gain control range of up to 45 dB was obtained with an insertion phase change of no more than + or 2 degrees for the first 10 dB of gain control.

Kim, B.↗
NASA NTRS1993

Characteristics of 0.8- and 0.2-microns gate length In(x)Ga(1-x) As/In(0.52)Al(0.48)As/InP (0.53 less than or equal to x less than or equal to 0.70) modulation-doped field-effect transistors at cryogenic temperatures

The performance characteristics of InP-based In(x)Ga(1-x)As/In(0.52)Al(0.48)As (0.53 is less than or equal to x is less than or equal to 0.70) pseudomorphic modulation-doped field-effect transistors (MODFET's) as a function of strain in the channel, gate, length, and temperature were investigated analytically and experimentally. The strain in the channel was varied by varying the In composition x. The temperature was varied in the range of 40-300 K and the devices have gate lengths L(sub g) of 0.8 and 0.2 microns. Analysis of the device was done using a one-dimensional self consistent solution of the Poisson and Schroedinger equations in the channel, a two-dimensional Poisson solver to obtain the channel electric field, and a Monte Carlo simulation to estimate the carrier transit times in the channel. An increase in the value of the cutoff frequency is predicted for an increase in In composition, a decrease in temperature, and a decrease in gate length. The improvements seen with decreasing temperature, decreasing gate length, and increased In composition were smaller than those predicted by analysis. The experimental results on pseudomorphic InGaAs/InAlAs MODFET's showed that there is a 15-30 percent improvement in cutoff frequency in both the 0.8- and 0.2-micron gate length devices when the temperature is lowered from 300 to 40 K.

Lai, Richard↗
NASA NTRS2003

Design of a Ferroelectric Programmable Logic Gate Array

A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.

MacLeod, Todd C.↗
NASA NTRS2006

Dual Input AND Gate Fabricated From a Single Channel Poly (3-Hexylthiophene) Thin Film Field Effect Transistor

A regio-regular poly (3-hexylthiophene) (RRP3HT) thin film transistor having a split-gate architecture has been fabricated on a doped silicon/silicon nitride substrate and characterized. This device demonstrates AND logic functionality. The device functionality was controlled by applying either 0 or -10 V to each of the gate electrodes. When -10 V was simultaneously applied to both gates, the device was conductive (ON), while any other combination of gate voltages rendered the device resistive (OFF). The p-type carrier charge mobility was about 5x10(exp -4) per square centimeter per V-sec. The low mobility is attributed to the sharp contours of the RRP3HT film due to substrate non-planarity. A significant advantage of this architecture is that AND logic devices with multiple inputs can be fabricated using a single RRP3HT channel with multiple gates.

Pinto, N. J.↗
NASA NTRS2009

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

Phillips, Thomas A.↗
NASA NTRS2009

Assessment of SOI AND Gate, Type CHT-7408, for Operation in Extreme Temperature Environments

Electronic parts based on silicon-on-insulator (SOI) technology are finding widespread applications due to their ability to operate in harsh environments and the benefits they offer as compared to their silicon counterparts. Due to their construction, they are tailored for high temperature operation and show good tolerance to radiation events. In addition, their inherent design lessens the formation of parasitic junctions, thereby reducing leakage currents, decreasing power consumption, and enhancing speed. These devices are typically rated in temperature capability from -55 C to about +225 C, and their characteristics over this temperature range are documented in data sheets. Since electronics in some of NASA space exploration missions are required to operate under extreme temperature conditions, both cold and hot, their characteristic behavior within the full temperature spectrum must be determined to establish suitability for use in space applications. The effects of extreme temperature exposure on the performance of a new commercial-off-the-shelf (COTS) SOI AND gate device were evaluated in this work. The high temperature, quad 2-inputs AND gate device, which was recently introduced by CISSOID, is fabricated using a CMOS SOI process. Some of the specifications of the CHT-7408 chip are listed in a table. By supplying a constant DC voltage to one gate input and a 10 kHz square wave into the other associated gate input, the chip was evaluated in terms of output response, output rise (t(sub r)) and fall times (tf), and propagation delays (using a 50% level between input and output during low to high (tPLH) and high to low (tPHL) transitions). The supply current of the gate circuit was also obtained. These parameters were recorded at various test temperatures between -195 C and +250 C using a Sun Systems environmental chamber programmed at a temperature rate of change of 10 C/min. In addition, the effects of thermal cycling on this chip were determined by exposing it to a total of 12 cycles between -195 C and +250 C. Following the cycling activity, measurements were performed again at the test temperatures of -195 C, +21 C, and +250 C.

Patterson, Richard↗
NASA NTRS2011

Characterization of a Common-Gate Amplifier Using Ferroelectric Transistors

In this paper, the empirical data collected through experiments performed using a FeFET in the common-gate amplifier circuit is presented. The FeFET common-gate amplifier was characterized by varying all parameters in the circuit, such as load resistance, biasing of the transistor, and input voltages. Due to the polarization of the ferroelectric layer, the particular behavior of the FeFET common-gate amplifier presents interesting results. Furthermore, the differences between a FeFET common-gate amplifier and a MOSFET common-gate amplifier are examined.

Hunt, Mitchell↗
NASA NTRS2019

Gate Drive Technology Evaluation and Development to Maximize Switching Speed of SiC Discrete Devices and Power Modules in Hard Switching Applications

To understand the limitation of maximizing the switching speed of SiC low current discrete devices and high current power modules in hard switching applications, double pulse tests are conducted and the testing results are analyzed. For power modules, the switching speed is generally limited by the parasitics rather than the gate drive capability. For the discrete SiC device, the conventional voltage source gate drive (VSG) is not sufficient to maximize the switching speed even if the external gate resistance is minimized. The limitation of existing current source gate drives (CSG) are analyzed, and a CSG dedicated for SiC discrete devices is proposed, which can provide constant current during the switching transient regardless of the high Miller voltage and large internal gate resistance. Compared with the conventional VSG, the proposed CSG achieves 67% faster turnon time and 50% turn-off time, and 68% reduction in switching loss at full load condition.

Handong Gui↗
DOE OSTI2025

Floquet-engineered fast SNAP gates in weakly coupled circuit-QED systems

Superconducting cavities with high quality factors, coupled to a fixed-frequency transmon, provide a state-of-the-art platform for quantum information storage and manipulation. The commonly used selective number-dependent arbitrary phase ( SNAP ) gate faces significant challenges in ultrahigh-coherence cavities, where the weak dispersive shifts necessary for preserving high coherence typically result in prolonged gate times. Here, in this work, we propose a protocol to achieve high-fidelity SNAP gates that are orders of magnitude faster than the standard implementation, surpassing the speed limit set by the bare dispersive shift. We achieve this enhancement by dynamically amplifying the dispersive coupling via sideband interactions, followed by quantum optimal control on the Floquet-engineered system. We also present a unified perturbation theory that explains both the gate acceleration and the associated benign drive-induced decoherence, corroborated by Floquet-Markov simulations. These results pave the way for the experimental realization of high-fidelity, selective control of weakly coupled, high-coherence cavities, and expanding the scope of optimal control techniques to a broader class of Floquet quantum systems.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2025

Investigation of the Effect of Gate Oxide Screening with Adjustment Pulse on Commercial SiC Power MOSFETs

This paper presents a method to recover the negative threshold voltage shift during high field gate oxide screening of 1.2 kV 4H-SiC MOSFETs with an additional adjustment gate voltage pulse. To reduce field failure rates of the MOSFETs in operation, manufacturers perform a screening treatment to remove devices with extrinsic defects in the oxide. Current gate oxide screening procedures are limited to oxide fields at or below ~9 MV/cm for short durations (<1 s), which is not enough to remove all the devices with extrinsic defects. The results show that by implementing a lower field gate pulse, the threshold voltage shift can be partially recovered, and therefore the maximum screening field and time can be increased. However, both the initial screening pulse and the adjustment pulse require careful calibration to prevent significant degradation of the device threshold voltage, on-resistance, interface state density, or intrinsic lifetime. With a well calibrated set of pulses, higher screening fields can be utilized without significantly damaging the devices. This leads to an improvement in the overall screening efficiency of the process, reducing the number of devices with extrinsic oxide defects entering the field, and improving the reliability of the SiC MOSFETs in operation.

42 ENGINEERING↗
NASA NTRSDate not supplied

DC Modeling of 4H-SiC JFET Gate Length Reduction at 500°C

The development of robust, high-performance integrated circuits (ICs) will enable numerous potential NASA missions of current interest, including long-duration robotic missions exploring the 460 °C surface of Venus. Currently, NASA is looking towards SiC-based devices to provide such a solution. However, the current NASA silicon carbide (SiC) JFET device with a channel length of 6μm (for recently fabricated Gen. 11 ICs) limits on mission relevant circuit capabilities [1]. In this study, we combined experiments with simulations to explore two straightforward fabrication strategies to reduce the SiC JFET channel length while maintaining turn-off behavior (Fig. 1a) needed to realize 500 °C circuit operation. The first fabrication strategy uses a shallow self-align nitrogen implant (Figure 1b) along the device's top surface but not below the gate combined with a high-dose phosphorous implant directly below the source and drain contacts. For the second fabrication strategy (Figure 1c), the high-dose phosphorous implants extended from below the contacts all the way up to the gate edges. Simulations guided gate length reductions without significant degradation in the turn-off performance. In total 12 SiC JFET variants implementing using the different fabrication strategies, gate lengths, and n-channel epilayer thickness were implemented in our simulation framework implemented in COMSOL. Since the COMSOL database does not have the material properties for 4H-SiC, these parameters were taken from the literature and implemented in COMSOL. The empirical models [2] for incomplete ionization, Auger recombination, low field mobility, and Shockley-Read-Hall recombination were implemented to account for material-specific device behavior.

4H-SiC JFET↗
DOE OSTI2026

Probing the Nanoscale Excitonic Landscape and Confinement of Excitons in Gated Monolayer Semiconductors

Engineering and probing excitonic properties at the nanoscale remains a central challenge in quantum photonics and optoelectronics. While exciton confinement via electrical control and strain engineering has been demonstrated in 2D semiconductors, substantial nanoscale heterogeneity limits the scalability of 2D quantum photonic device architectures. Here, in this work, we use cathodoluminescence spectroscopy to probe the excitonic landscape of monolayer WS 2 under electrostatic gating. Exploiting the high spatial resolution of the converged electron beam, we resolve a homojunction arising between gated and ungated regions. Moreover, we reveal an exciton confinement channel arising from an unconventional doping mechanism driven by the interplay between the electron beam and the applied gate fields. These findings offer new insights into the optoelectronic behavior of monolayer semiconductors under the combined influence of electron-beam excitation and electrostatic gating. Our approach provides a pathway for exciton manipulation at the nanoscale and opens opportunities for controlling quantum-confined exciton transport in 2D materials.

2D materials↗
DOE OSTI2024

Quantitative modeling of gate-tunable cavity exciton-polaritons in transition-metal dichalcogenides

We performed a comprehensive real-space simulation study of propagative exciton-polaritons (EPs) of tungsten disulfide (WS 2 ) inside a Fabry–Pérot cavity. Through our simulations, we were able to construct the dispersion relation and determine the propagation length (L p ) of EPs, both of which show sensitive dependence on the applied gate voltage. We found that L p increases at higher gate voltages when excited at the exciton energy but shows opposite gate dependence at the trion energy. These observations are direct evidence of the coupling between the cavity mode with excitons and trions of WS 2 . Furthermore, we demonstrate a proof-of-concept device based on the tunable cavity EPs of WS 2 , which is promising for application as photonic transistors, modulators, or electrical-to-optical converters. Furthermore, our work unveils the real-space transport properties of gate-tunable cavity EPs and paves the way for future applications of EPs in nanophotonic devices and circuits.

42 ENGINEERING↗
DOE OSTI2025

In situ synchrotron x-ray studies of epitaxial SrCoO x films during ionic liquid gating

The manipulation of ions in complex oxide materials can be used to mimic brain-like plasticity through changes to the resistivity of a neuromorphic device. Advances in the design of more energy efficient devices require improved understanding of how ions migrate within a material and across its interface. We investigate the exchange of oxygen and hydrogen in a model SrCoO x epitaxial film—a material that transitions between a ferromagnetic metal and antiferromagnetic insulator depending on the oxygen concentration. Changes to the film during ionic liquid gating were measured by in situ synchrotron x-ray techniques as a function of time and gate voltage, examining the reversibility of the oxide over one complete gating cycle. We find that the out-of-plane lattice constant and oxygen vacancy concentration of SrCoO x are largely reversible although changes were observed in the ordered vacancy structure. Our results provide much needed insight into electrolyte-gated phase behavior in the transition metal oxides.

Li, Yan [Argonne National Laboratory (ANL), Argonn↗
DOE OSTI2025

Synthesis of single-qutrit circuits from Clifford+𝑅 gates

Here, we present two deterministic compilation algorithms for single-qutrit unitaries with O ( log 1 / ɛ ) gate depth. Each algorithm selects a nearby approximation to the target unitary and then exactly synthesizes the approximation over the Clifford + R basis. The first algorithm exhaustively searches over the group; while the second algorithm searches only for Householder reflections. The exhaustive search algorithm yields an average R count of 2.193 ( 11 ) + 8.621 ( 7 ) log 10 ( 1 / ɛ ) , albeit with a time complexity of O ( ɛ − 4.4 ) . The Householder search algorithm results in a larger average R count of 3.20 ( 13 ) + 10.77 ( 3 ) log 10 ( 1 / ɛ ) at a reduced time complexity of O ( ɛ − 0.42 ) , greatly extending the reach in ɛ . These costs correspond asymptotically to 35% and 69% more non-Clifford gates compared with synthesizing the same unitary with two qubits. Such initial results are encouraging for using the R gate as the nontransversal gate for qutrit-based computation.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2026

Clifford Hierarchy Stabilizer Codes: Transversal Non-Clifford Gates and Magic States

A fundamental problem in fault-tolerant quantum computation is the tradeoff between universality and dimensionality, exemplified by the the Bravyi-König bound for $n$-dimensional topological stabilizer codes. In this work, we extend topological Pauli stabilizer codes to a broad class of $n$-dimensional Clifford hierarchy stabilizer codes. These codes correspond to the $(n+1)$D Dijkgraaf-Witten gauge theories with non-Abelian topological order. We construct transversal non-Clifford gates through automorphism symmetries represented by cup products. In 2D, we obtain the first transversal non-Clifford logical gates including T and CS for Clifford stabilizer codes, using the automorphism of the twisted $\mathbb{Z}_2^3$ gauge theory (equivalent to $\mathbb{D}_4$ topological order). We also combine it with the just-in-time decoder to fault-tolerantly prepare the logical T magic state in $O(d)$ rounds via code switching. In 3D, we construct a transversal logical $\sqrt{\text{T}}$ gate in a non-Clifford stabilizer code at the third level of the Clifford hierarchy, located on a tetrahedron corresponding to a twisted $\mathbb{Z}_2^4$ gauge theory. Furthermore, our constructions surpass the Bravyi-König bound by achieving the logical gates in the $(n+1)$-th level of Clifford hierarchy in $n$ spatial dimension.

Kobayashi, Ryohei [Institute for Advanced Study, P↗