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Results for “semiconductor fabrication”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
NASA NTRS1979

Semiconductor structure

A technique for fabricating a semiconductor heterostructure by growth of a ternary semiconductor on a binary semiconductor substrate from a melt of the ternary semiconductor containing less than saturation of at least one common ingredient of both the binary and ternary semiconductors wherein in a single temperature step the binary semiconductor substrate is etched, a p-n junction with specific device characteristics is produced in the binary semiconductor substrate by diffusion of a dopant from the melt and a region of the ternary semiconductor of precise conductivity type and thickness is grown by virtue of a change in the melt characteristics when the etched binary semiconductor enters the melt.

Hovel, Harold J.↗
DOE OSTI2020

Surface photovoltage spectroscopy observes junctions and carrier separation in gallium nitride nanowire arrays for overall water-splitting

Gallium nitride (GaN) nanowire arrays on silicon are able to drive the overall water-splitting reaction with up to 3.3% solar-to-hydrogen efficiency. Photochemical charge separation is key to the operation of these devices, but details are difficult to observe experimentally because of the number of components and interfaces. Here, we use surface photovoltage spectroscopy to study charge transfer in i-, n-, and p-GaN nanowire arrays on n+ -Si wafers in the presence and absence of Rh/Cr 2 O 3 co-catalysts. The effect of the space charge layer and sub-bandgap defects on majority and minority carrier transport can be clearly observed, and estimates of the built-in potential of the junctions can be made. Transient illumination of the p-GaN/n + -Si junction generates up to -1.4 V surface photovoltage by carrier separation along the GaN nanowire axis. This process is central to the overall water-splitting function of the n + -Si/p-GaN/Rh/Cr 2 O 3 nanowire array. Overall, these results improve our understanding of photochemical charge transfer and separation in group III–V semiconductor nanostructures for the conversion of solar energy into fuels.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2022

Pit rim decomposition into multiple quantum dots on surfaces of epitaxial thin films grown on pit-patterned substrates

Here, we report results of dynamical simulations according to an experimentally validated surface morphological evolution model on the formation of regular arrays of quantum dot molecules (QDMs) consisting of 1D arrays of smaller interacting quantum dots (QDs). These QD arrays form along the sides of each pit rim on the surface of a coherently strained thin film epitaxially deposited on a semiconductor substrate, the surface of which consists of a periodic pattern of inverted prismatic pits with rectangular pit openings. We find that this complex QDM pattern results from the decomposition of the pit rim from a “quantum fortress” with four elongated QDs into four 1D arrays of multiple smaller QDs arranged along each side of the pit rim. Systematic parametric analysis indicates that varying the pit opening dimensions and the pit wall inclination directly impacts the number of QDs in the resulting QDM pattern, while varying the pit depth only affects the dimensions of the QDs in the nanostructure pattern. Therefore, the number, arrangement, and sizes of QDs in the resulting pattern of QDMs on the film surface can be engineered precisely by proper tuning of the pit design parameters. Our simulation results are supported by predictions of morphological stability analysis, which explains the pit rim decomposition into multiple QDs as the outcome of a tip-splitting instability and provides a fundamental characterization of the post-instability nanostructure pattern. Our theoretical findings can play a vital role in designing optimal semiconductor surface patterns toward enabling future nanofabrication technologies.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Controlled Dielectric Breakdown to Form Pinhole Passivating Contacts

This contribution explores an alternate route to forming pinhole-based poly-Si/dielectric/c-Si passivating contacts. The method utilizes controlled dielectric breakdown or electroforming to produce nanoscale pinholes in a thick (non-tunnelling) dielectric which, when annealed, allows dopant atoms to pass from doped poly-Si through the pinholes and into the c-Si wafer, forming conductive pathways. We show that the pinholes lose passivation after electroforming but can be repassivated with a forming gas anneal. N-type contacts show contact resistivities of ~20 mOhm-cm2, but p-type contacts are ~100 mOhm-cm2. Devices show a distinct kink in the J-V curve indicative of a barrier to transport. The method can be expanded to optimized dielectric passivation stacks (not just thin, single layers) and can be formed in parallel over the faces of the wafer in selected areas (pinholes only under the grid lines).

CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND SU↗
DOE OSTI2024

Dislocation half-loop control for optimal V-defect density in GaN-based light emitting diodes

V-defects are morphological defects that typically form on threading dislocations during epitaxial growth of $(0001)$-oriented GaN layers. A V-defect is a hexagonal pyramid-shaped depression with six {$10\bar{1}1$}-oriented sidewalls. These semipolar sidewalls have a lower polarization barrier than the polarization barriers present between the polar c-plane quantum wells and quantum barriers and can laterally inject carriers directly into quantum wells in GaN-based light emitting diodes (LEDs). This is especially important, as the high polarization field in c-plane GaN is a significant factor in the high forward voltage of GaN LEDs. The optimal V-defect density for efficient lateral carrier injection in a GaN LED (∼10 9 cm −2 ) is typically an order of magnitude higher than the threading dislocation density of GaN grown on patterned sapphire substrates (∼10 8 cm −2 ). Pure-edge dislocation loops have been known to exist in GaN, and their formation into large V-defects via low-temperature growth with high Si-doping has recently been studied. Here, in this work, we develop a method for pure-edge threading dislocation half-loop formation and density control via disilane flow, growth temperature, and thickness of the half-loop generation layer. We also develop a method of forming the threading dislocation half-loops into V-defects of comparable size to those originating from substrate threading dislocations.

Crystallographic defects↗
NASA NTRS1992

Scheduling revisited workstations in integrated-circuit fabrication

The cost of building new semiconductor wafer fabrication factories has grown rapidly, and a state-of-the-art fab may cost 250 million dollars or more. Obtaining an acceptable return on this investment requires high productivity from the fabrication facilities. This paper describes the Photo Dispatcher system which was developed to make machine-loading recommendations on a set of key fab machines. Dispatching policies that generally perform well in job shops (e.g., Shortest Remaining Processing Time) perform poorly for workstations such as photolithography which are visited several times by the same lot of silicon wafers. The Photo Dispatcher evaluates the history of workloads throughout the fab and identifies bottleneck areas. The scheduler then assigns priorities to lots depending on where they are headed after photolithography. These priorities are designed to avoid starving bottleneck workstations and to give preference to lots that are headed to areas where they can be processed with minimal waiting. Other factors considered by the scheduler to establish priorities are the nearness of a lot to the end of its process flow and the time that the lot has already been waiting in queue. Simulations that model the equipment and products in one of Texas Instrument's wafer fabs show the Photo Dispatcher can produce a 10 percent improvement in the time required to fabricate integrated circuits.

Kline, Paul J.↗
DOE OSTI2020

Using a carbon vacancy reduction material to increase average carrier lifetime in a silicon carbide semiconductor device

A semiconductor die and a process for fabricating the semiconductor die are disclosed. The semiconductor die has a substrate and a silicon carbide (SiC) epitaxial structure on the substrate. The SiC epitaxial structure includes at least a first N-type SiC layer, at least a first P-type SiC layer, and carbon vacancy reduction material, which has been implanted into a surface of the SiC epitaxial structure. Further, the SiC epitaxial structure has been annealed to mobilize the carbon vacancy reduction material to diffuse carbon atoms substantially throughout the SiC epitaxial structure, thereby increasing an average carrier lifetime in the SiC epitaxial structure.

36 MATERIALS SCIENCE↗
NASA NTRS1990

Method of fabricating germanium and gallium arsenide devices

A method of semiconductor diode fabrication is disclosed which relies on the epitaxial growth of a precisely doped thickness layer of gallium arsenide or germanium on a semi-insulating or intrinsic substrate, respectively, of gallium arsenide or germanium by either molecular beam epitaxy (MBE) or by metal-organic chemical vapor deposition (MOCVD). The method involves: depositing a layer of doped or undoped silicon dioxide on a germanium or gallium arsenide wafer or substrate, selectively removing the silicon dioxide layer to define one or more surface regions for a device to be fabricated thereon, growing a matched epitaxial layer of doped germanium or gallium arsenide of an appropriate thickness using MBE or MOCVD techniques on both the silicon dioxide layer and the defined one or more regions; and etching the silicon dioxide and the epitaxial material on top of the silicon dioxide to leave a matched epitaxial layer of germanium or gallium arsenide on the germanium or gallium arsenide substrate, respectively, and upon which a field effect device can thereafter be formed.

Jhabvala, Murzban↗
NASA NTRS1978

Multilevel metallization method for fabricating a metal oxide semiconductor device

An improved method is described of constructing a metal oxide semiconductor device having multiple layers of metal deposited by dc magnetron sputtering at low dc voltages and low substrate temperatures. The method provides multilevel interconnections and cross over between individual circuit elements in integrated circuits without significantly reducing the reliability or seriously affecting the yield.

Hollis, B. R., Jr.↗
NASA NTRS2018

Index-Coupled Distributed-Feedback Semiconductor Quantum Cascade Lasers Fabricated Without Epitaxial Regrowth

Quantum cascade (QC) lasers and methods of fabricating such QC lasers are provided. The QC lasers incorporate a DFB grating without requiring the use of relying on epitaxial regrowth processes. The DFB gratings are formed as sidewall gratings along the lateral length of the QC active region, or the DFB gratings are formed atop the lateral length of the QC active region, and wherein the top DFB grating is planarized with a polymeric material.

Briggs, Ryan M.↗
NASA NTRS1993

Curved grating fabrication techniques for concentric-circle grating, surface-emitting semiconductor lasers

We describe the fabrication and operational characteristics of a novel, surface-emitting semiconductor laser that makes use of a concentric-circle grating to both define its resonant cavity and to provide surface emission. A properly fabricated circular grating causes the laser to operate in radially inward- and outward-going circular waves in the waveguide, thus, introducing the circular symmetry needed for the laser to emit a beam with a circular cross-section. The basic circular-grating-resonator concept can be implemented in any materials system; an AlGaAs/GaAs graded-index, separate confinement heterostructure (GRINSCH), single-quantum-well (SQW) semiconductor laser, grown by molecular beam epitaxy (MBE), was used for the experiments discussed here. Each concentric-circle grating was fabricated on the surface of the AlGaAs/GaAs semiconductor laser. The circular pattern was first defined by electron-beam (e-beam) lithography in a layer of polymethylmethacrylate (PMMA) and subsequently etched into the semiconductor surface using chemically-assisted (chlorine) ion-beam etching (CAIBE). We consider issues that affect the fabrication and quality of the gratings. These issues include grating design requirements, data representation of the grating pattern, and e-beam scan method. We provide examples of how these techniques can be implemented and their impact on the resulting laser performance. A comparison is made of the results obtained using two fundamentally different electron-beam writing systems. Circular gratings with period lambda = 0.25 microns and overall diameters ranging from 80 microns to 500 microns were fabricated. We also report our successful demonstration of an optically pumped, concentric-circle grating, semiconductor laser that emits a beam with a far-field divergence angle that is less than one degree. The emission spectrum is quite narrow (less than 0.1 nm) and is centered at wavelength lambda = 0.8175 microns.

Jordan, Rebecca H.↗
NASA NTRS1993

Laboratory experiments in integrated circuit fabrication

The objectives of the experiment are fourfold: to provide practical experience implementing the fundamental processes and technology associated with the science and art of integrated circuit (IC) fabrication; to afford the opportunity for the student to apply the theory associated with IC fabrication and semiconductor device operation; to motivate the student to exercise engineering decisions associated with fabricating integrated circuits; and to complement the theory of n-channel MOS and diffused devices that are presented in the classroom by actually fabricating and testing them. Therefore, a balance between theory and practice can be realized in the education of young engineers, whose education is often criticized as lacking sufficient design and practical content.

Jenkins, Thomas J.↗
DOE OSTI2020

Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad

According to the continuous development of metal-oxide semiconductor (MOS) fabrication technology, transistors have naturally become more radiation-tolerant through steadily decreasing gate-oxide thickness, increasing the tunneling probability between gate-oxide and channel. Unfortunately, despite this radiation-hardened property of developed transistors, the field of nuclear power plants (NPPs) requires even higher radiation hardness levels. Particularly, total ionizing dose (TID) of approximately 1 Mrad could be required for readout circuitry under severe accident conditions with 100 Mrad around a reactor in-core required. In harsh radiating environments such as NPPs, sensors such as micro-pocket-fission detectors (MPFD) would be a promising technology to be operated for detecting neutrons in reactor cores. For those sensors, readout circuits should be fundamentally placed close to sensing devices for minimizing signal interferences and white noise. Therefore, radiation hardening ability is necessary for the circuits under high radiation environments. This paper presents various integrated circuit designs for a radiation hardened charge-sensitive amplifier (CSA) by using SiGe 130 nm and Si 180 nm fabrication processes with different channel widths and transistor types of complementary metal-oxide-semiconductor (CMOS) and bipolar CMOS (BiCMOS). These circuits were tested under γ–ray environment with Cobalt-60 of high level activity: 490 kCi. The experiment results indicate amplitude degradation of 2.85%–34.3%, fall time increase of 201–1730 ns, as well as a signal-to-noise ratio (SNR) of 0.07–11.6 dB decrease with irradiation dose increase. These results can provide design guidelines for radiation hardening operational amplifiers in terms of transistor sizes and structures.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
NASA NTRS2001

On the Fabrication and Behavior of Diamond Microelectromechanical Sensors (DMEMS)

CVD (chemically vapor deposited) diamond films can be processed similar to "conventional" semiconductor device fabrication and as such can be used to achieve microelectromechanical structures (MEMS) also similar to, for example, silicon technology. Very small cantilever beams, membranes, stripes, tips, etc. can be constructed in doped and undoped diamond films and offer an array of choices in diamond with its known superior properties such as elastic modulus, high temperature semiconduction, high thermal conductivity, very low coefficient of expansion and numerous other diamond parameters. This paper will review the construction and behavior of the second generation DMEMS devices comprised as an accelerometer with a diamond diaphragm for use in very high G applications and a diamond pressure sensor for very high temperature and frequency response.

Holmes, K.↗
NASA NTRS2000

Monolithic integrated high-T.sub.c superconductor-semiconductor structure

A method for the fabrication of active semiconductor and high-temperature superconducting device of the same substrate to form a monolithically integrated semiconductor-superconductor (MISS) structure is disclosed. A common insulating substrate, preferably sapphire or yttria-stabilized zirconia, is used for deposition of semiconductor and high-temperature superconductor substructures. Both substructures are capable of operation at a common temperature of at least 77 K. The separate semiconductor and superconductive regions may be electrically interconnected by normal metals, refractory metal silicides, or superconductors. Circuits and devices formed in the resulting MISS structures display operating characteristics which are equivalent to those of circuits and devices prepared on separate substrates.

Burns, Michael J.↗