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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
NASA NTRS2019

Mechanisms of Heavy Ion-Induced Single Event Burnout in 4H-SiC Power MOSFETs

This describes the mechanisms behind the failure of 4H-SiC Power MOSFETs when struck by a heavy ion. The modeled device is designed to simulate a commercially available 1200 V power MOSFET and the ion simulated is a silver ion with a Linear Energy Transfer of 46 MeV-cm2/mg commonly used in single event effect (SEE) testing. The device is shown in simulation to fail near 500 V, which is in close agreement to experiments. These simulations go to show that the failure of SiC MOSFET occurs near the interface between the epi and substrate layers due to the rapid increase of the electric field in that region and destruction of the device from impact ionization. From this, two designs were proposed and investigated that would help to mitigate the electric field in these regions and improve the device's tolerance to single-event burnout (SEB). The new designs increased the voltage at which SEB occurs from 500 V to over 900 V and increased the Ron,sp by only 5%.

Mcpherson, Joseph A.↗
DOE OSTI2023

Achieving Single-Electron Sensitivity at Enhanced Speed in Fully-Depleted CCDs with Double-Gate MOSFETs

We introduce a new output amplifier for fully-depleted thick p-channel CCDs based on double-gate MOSFETs. The charge amplifier is an n-type MOSFET specifically designed and operated to couple the fully-depleted CCD with high charge-transfer efficiency. The junction coupling between the CCD and MOSFET channels has enabled high sensitivity, demonstrating sub-electron readout noise in one pixel charge measurement. We have also demonstrated the non-destructive readout capability of the device. Achieving single-electron and single-photon per pixel counting in the entire CCD pixel array has been made possible through the averaging of a small number of samples. We have demonstrated fully-depleted CCD readout with better performance than the floating diffusion and floating gate amplifiers available today, in both single and multisampling regimes, boasting at least six times the speed of floating gate amplifiers.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

Radiation Response of Ga 2 O 3 MOSFETs Probed via Focused Particle Beams

Gallium Oxide (Ga 2 O 3 ), particularly in its β-phase, is attracting lots of interest for high-power and high-voltage electronics due to its wide bandgap, high breakdown field, and thermal stability. This study investigates the radiation response of Ga 2 O 3 Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) under Total Ionizing Dose (TID) and Displacement Damage (DD) conditions, which are critical for applications in radiation environments. Utilizing a dual-beam Focused Ion Beam and Scanning Electron Microscope setup, microscale analysis of radiation effects on individual devices is performed. The findings reveal distinct behaviors under TID and DD + TID conditions, with TID leading to threshold voltage shifts due to trapped charges, while DD results in decreased drive current attributed to increased carrier scattering from lattice defects. Notably, it is demonstrated that the TID effect can be mitigated through dynamic threshold voltage adjustments and that the predicted TID from ions calculated by Monte Carlo simulations overestimates actual TID due to unaccounted charge yield effects. In conclusion, this research enhances the understanding of Ga2O3 MOSFETs' performance in harsh radiation environments, providing insights for the design of robust electronic devices for space and nuclear applications.

MOSFET↗
DOE OSTI2019

Aperiodic graphene ribbons in MOSFET topology for multi-wavelength terahertz generation

This paper proposes and simulates multi-wavelength terahertz wave generation using MOSFET with aperiodic gate structure. This emitter works at room temperature and spans the whole terahertz spectra. Structure of the emitter is like a MOSFET for which the channel and gate respectively consist of periodic and aperiodic graphene ribbons. By applying a DC voltage to the source and drain contacts, a DC current flows through the periodic channel. Then by applying a gate voltage to aperiodic graphene ribbons, the current is modulated with aperiodic graphene potential of the gate. The gate voltage applies aperiodic potential U(x) to channel’s electrons that subsequently modulates current of the periodic channel. The modulated current radiates coherent electromagnetic waves. By tuning parameters of the emitter, the radiated coherent electromagnetic wave is in THz range.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2018

Exploring the Short-Channel Characteristics of Asymmetric Junctionless Double-Gate Silicon-on-Nothing MOSFET

This paper presents an analytical model of an asymmetric junctionless double-gate (asymmetric DGJL) silicon-on-nothing metal-oxide-semiconductor field-effect transistor (MOSFET). Solving the 2-D Poisson’s equation, the expressions for center potential and threshold voltage are calculated. In addition, the response of the device toward the various short-channel effects like hot carrier effect, drain-induced barrier lowering and threshold voltage roll-off has also been examined along with subthreshold swing and drain current characteristics. Performance analysis of the present model is also demonstrated by comparing its short-channel behavior with conventional DGJL MOSFET. The effect of variation of the device features due to the variation of device parameters is also studied. The simulated results obtained using 2D device simulator, namely ATLAS, are in good agreement with the analytical results, hence validating our derived model.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

Interface defects in SiC power MOSFETs - An electrically detected magnetic resonance study based on spin dependent recombination

This study presents electrically detected magnetic resonance (EDMR) measurements on a silicon carbide (SiC) MOSFET having the structure of a double-diffused silicon MOSFET (DMOS). The resonance pattern of a SiC DMOS was measured by monitoring the change of the recombination current between the source/body and the drain. The amplitude of the response has a maximum when the device is biased in depletion due to the equal concentrations of electrons and holes at the interface resulting in the most efficient recombination. The measured anisotropic g-tensor has axial symmetry with g{sub ∥} = 2.0051(4) (B ‖ c-axis), and g{sub ⊥} = 2.0029(4) (B⊥ c-axis) and the pattern shows several hyperfine (HF) peaks. We tentatively identify the observed defect as a silicon vacancy located directly at the interface.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

Nanosecond pulsed electric fields (nsPEFs) low cost generator design using power MOSFET and Cockcroft-Walton multiplier circuit as high voltage DC source

Purpose: Non-ionizing radiation therapy for cancer using pulsed electric field with high intensity field has become an interesting field new research topic. A new method using nanosecond pulsed electric fields (nsPEFs) offers a novel means to treat cancer. Not like the conventional electroporation, nsPEFs able to create nanopores in all membranes of the cell, including membrane in cell organelles, like mitochondria and nucleus. NsPEFs will promote cell death in several cell types, including cancer cell by apoptosis mechanism. NsPEFs will use pulse with intensity of electric field higher than conventional electroporation, between 20–100 kV/cm and with shorter duration of pulse than conventional electroporation. NsPEFs requires a generator to produce high voltage pulse and to achieve high intensity electric field with proper pulse width. However, manufacturing cost for creating generator that generates a high voltage with short duration for nsPEFs purposes is highly expensive. Hence, the aim of this research is to obtain the low cost generator design that is able to produce a high voltage pulse with nanosecond width and will be used for nsPEFs purposes. Method: Cockcroft-Walton multiplier circuit will boost the input of 220 volt AC into high voltage DC around 1500 volt and it will be combined by a series of power MOSFET as a fast switch to obtain a high voltage with nanosecond pulse width. The motivation using Cockcroft-Walton multiplier is to acquire a low-cost high voltage DC generator; it will use capacitors and diodes arranged like a step. Power MOSFET connected in series is used as voltage divider to share the high voltage in order not to damage them. Results: This design is expected to acquire a low-cost generator that can achieve the high voltage pulse in amount of −1.5 kV with falltime 3 ns and risetime 15 ns into a 50Ω load that will be used for nsPEFs purposes. Further detailed on the circuit design will be explained at presentation.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2019

Self-Powering High Frequency Modulated SiC Power MOSFET Isolated Gate Driver

A novel implementation of an isolated gate driver for power switches is proposed in this study. The driver is bespoke designed for SiC power mosfet s. The proposal achieves the main driver characteristics—isolation capability, gate switching command, and power transfer to the secondary side by using a unique magnetic transformer. The resulting simple circuitry enables the integration of the driver into the power cell, achieving theoretical higher power density values of the final system. The principle of operation of the driver is described in detail. The original pulsewidth modulation signal is modulated with a pure ac square waveform under a two-level modulation scheme, that guarantees no saturation of the magnetic core. Here, the signal is then magnetically coupled to the secondary side, where it is rectified and reconstructed to effectively drive the target device. In addition, the steps needed to provide a suitable design taking into account the parameters of the target power switch are also detailed. The resulting driver is characterized and a prototype of the driver is built and tested. The main results of the driver performance on a SiC mosfet -based prototype are presented. Based on the analysis of these results, this study experimentally demonstrates the feasibility of the proposal.

25 ENERGY STORAGE↗
DOE OSTI2017

On Developing One-Chip Integration of 1.2 kV SiC MOSFET and JBS Diode (JBSFET)

This paper presents the design, fabrication, and characterization of the SiC JBSFET (JBS diode integrated MOSFET). The fabrication of the JBSFET adopted a novel single metal, single thermal treatment process to simultaneously form ohmic contacts on n+, p+ implanted regions, and Schottky contact on the n- 4H-SiC epi-layer. The presented SiC JBSFET uses 40% smaller wafer area because the diode and MOSFET share the edge termination as well as the current conducting drift region. Here, the proposed single chip solution of MOSFET/JBS diode functionalities eliminates the parasitic inductance between separately packaged devices allowing a higher frequency operation in a power converter.

42 ENGINEERING↗
DOE OSTI2014

A High Temperature Silicon Carbide mosfet Power Module With Integrated Silicon-On-Insulator-Based Gate Drive

Here we present a board-level integrated silicon carbide (SiC) MOSFET power module for high temperature and high power density application. Specifically, a silicon-on-insulator (SOI)-based gate driver capable of operating at 200°C ambient temperature is designed and fabricated. The sourcing and sinking current capability of the gate driver are tested under various ambient temperatures. Also, a 1200 V/100 A SiC MOSFET phase-leg power module is developed utilizing high temperature packaging technologies. The static characteristics, switching performance, and short-circuit behavior of the fabricated power module are fully evaluated at different temperatures. Moreover, a buck converter prototype composed of the SOI gate driver and SiC power module is built for high temperature continuous operation. The converter is operated at different switching frequencies up to 100 kHz, with its junction temperature monitored by a thermosensitive electrical parameter and compared with thermal simulation results. The experimental results from the continuous operation demonstrate the high temperature capability of the power module at a junction temperature greater than 225°C.

36 MATERIALS SCIENCE↗
DOE OSTI2018

Short-Circuit Characterization and Protection of 10-kV SiC mosfet

This paper presents the characterization of the temperature-dependent short-circuit performance of a Gen3 10 kV/20 A silicon carbide (SiC) mosfet. The test platform consisting of a phase-leg configuration and a fast speed 10-kV solid state circuit breaker, with temperature control, is introduced in detail. A novel FPGA-based short-circuit protection circuit having a response time of 1.5 μs is proposed and integrated into the gate driver. The short-circuit protection is validated through the platform. The short-circuit characteristics for both the hard switching fault and fault under load (FUL) types at various dc-link voltages (from 500 V to 6 kV) are tested and discussed. The saturation current increases with dc-link voltage and achieves 360 A at 6 kV. Different from low voltage SiC devices, there is no current spike in FUL type of fault. The temperature-dependent short-circuit performance is also presented from 25 to 125 °C. The difference of short-circuit waveforms at various initial junction temperatures can be neglected. Here, a thermal model of the 10-kV SiC mosfet is built for the junction temperature estimation during the short circuit and for analysis of the initial junction temperature impact on the short-circuit performance.

10-kV SiC mosfet↗
DOE OSTI2012

An analytical gate tunneling current model for MOSFETs

Gate tunneling current of MOSFETs is an important factor in modeling ultra small devices. In this paper, gate tunneling in present-generation MOSFETs is studied. In the proposed model, we calculate the electron wave function at the semiconductor-oxide interface and inversion charge by treating the inversion layer as a potential well, including some simplifying assumptions. Then we compute the gate tunneling current using the calculated wave function. The proposed model results have an excellent agreement with experimental results in the literature.

36 MATERIALS SCIENCE↗
DOE OSTI2018

On the Spatial Localization of Free Electrons in 4H-SiC MOSFETS with an n Channel

The problem of the spatial localization of free electrons in 4H-SiC metal—oxide—semiconductor field effect transistors (MOSFETS) with an accumulation- and inversion-type n channel is theoretically analyzed. The analysis demonstrates that, in optimally designed accumulation transistors (ACCUFETs), the average distance from the surface, at which free electrons are localized, may be an order of magnitude larger than that in inversion MOSFETs. This can make 4H-SiC ACCUFETs advantageous as regards the effective carrier mobility in a conducting channel.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2021

A Study of Integrated Signal and Power Transfer for Compact Isolated SiC MOSFET Gate-Drivers

This work discusses a novel set of alternate implementations of isolated gate driver circuits for power electronic transistors. The proposed topologies for the driver have been designed specifically for SiC power MOSFET. Three different solutions are discussed, all of them providing the required gate turn-on and turn-off command signal with galvanic isolation, but also supplying power to the secondary side of the driver by means of magnetic transformers. The resulting solutions, all of them implemented with simple circuitry, enable the integration of the driver into the power cell, allowing for theoretical higher power density values in the final system. The principle of operation of the different solutions is discussed, and then the main relevant implementation details are presented. After that, the operation of the circuits is demonstrated experimentally, by testing a set of prototypes of these drivers. This provides a comprehensive design example that assesses the feasibility of the proposed solutions. Finally, the main results of the performance of the three gate drivers, on an SiC MOSFET-based prototype are presented and compared.

42 ENGINEERING↗
NASA NTRS2018

Reliability Concerns for Flying SiC Power MOSFETs in Space

SiC power MOSFETs are space-ready in terms of typical reliability measures. However, single event burnout (SEB) often occurs at voltages 50% or lower than specified breakdown. Data illustrating burnout for 1200 V devices is reviewed and the space reliability of SiC MOSFETs is discussed.

Single-event burnout↗
NASA NTRS2018

Reliability Concerns for Flying SiC Power MOSFETs in Space

SiC power MOSFETs are space-ready in terms of typical reliability measures. However, single event burnout (SEB) often occurs at voltages 50% or lower than specified breakdown. Data illustrating burnout for 1200 V devices is reviewed and the space reliability of SiC MOSFETs is discussed.

silicon carbide↗
DOE OSTI2018

Trends in SiC MOSFET Threshold Voltage and ON-Resistance Measurements from Thermal Cycling and Electrical Switching Stresses: Preprint

Integrating SiC power MOSFETs is very attractive for advancing power electronic systems, yet the system reliability with new devices remains in question. This work presents two accelerated test experiments to further investigate the packaging and semiconductor failures of a TO-247 SiC MOSFET. First, a variation on power cycling experiments -- switching cycling -- is introduced. Traditional power cycling experiments utilize conduction losses to self-heat the device where a large temperature swing causes degradation at the packaging level. However, by decreasing the on-time such that the device only turns on and immediately turns off, the temperature swing is decreased and the semiconductor itself is degraded. This work shows experimental device degradation caused by continuous switching events - switching cycling, at 90% of the device's breakdown voltage. Second, thermal cycling experiments were conducted between -40 degrees C and 175 degrees C to observe degradation in the mechanical packaging of the device. Experimentally-measured changes in threshold voltage and ON-resistance are recorded in both experiments and compared. These results also illustrate the spectrum between device and package degradation from accelerated test methods.

33 ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2018

Hardware Design of a 1.7 kV SiC MOSFET Based MMC for Medium Voltage Motor Drives

Abstract—This paper presents the hardware design of a 7 kV dc bus,1 MVA, 0-1,000 Hz, 1.7 kV SiC MOSFET based medium voltage variable speed drive (MVVSD)1. The system is based on a 7-level three-phase modular multilevel converter (MMC). The full in-depth design, development, and testing of this prototype are provided, including MMC submodule development, arm inductor design, control hardware realization, system integration and thermal analysis. Finally, experimental results demonstrate the excellent performance of the 1.7 kV SiC MOSFET based submodule and the 1 MW, 7 kV MVVSD as a unity in various operation modes

SiC MOSFET, Modular Multilevel Converter, Medium V↗