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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
NASA NTRS2011

Four-gate transistor analog multiplier circuit

A differential output analog multiplier circuit utilizing four G.sup.4-FETs, each source connected to a current source. The four G.sup.4-FETs may be grouped into two pairs of two G.sup.4-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G.sup.4-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed.

Mojarradi, Mohammad M.↗
NASA NTRS1977

Semicustom integrated circuits and the standard transistor array radix (STAR)

The development, application, pros and cons of the semicustom and custom approach to the integration of circuits are described. Improvements in terms of cost, reliability, secrecy, power, and size reduction are examined. Also presented is the standard transistor array radix, a semicustom approach to digital integrated circuits that offers the advantages of both custom and semicustom approaches to integration.

Edge, T. M.↗
NASA NTRS1981

Push-pull converter with energy saving circuit for protecting switching transistors from peak power stress

In a push-pull converter, switching transistors are protected from peak power stresses by a separate snubber circuit in parallel with each comprising a capacitor and an inductor in series, and a diode in parallel with the inductor. The diode is connected to conduct current of the same polarity as the base-emitter juction of the transistor so that energy stored in the capacitor while the transistor is switched off, to protect it against peak power stress, discharges through the inductor when the transistor is turned on, and after the capacitor is discharges through the diode. To return this energy to the power supply, or to utilize this energy in some external circuit, the inductor may be replaced by a transformer having its secondary winding connected to the power supply or to the external circuit.

Mclyman, W. T.↗
NASA NTRS1991

Asynchronous sequential circuit design using pass transistor iterative logic arrays

The iterative logic array (ILA) is introduced as a new architecture for asynchronous sequential circuits. This is the first ILA architecture for sequential circuits reported in the literature. The ILA architecture produces a very regular circuit structure. Moreover, it is immune to both 1-1 and 0-0 crossovers and is free of hazards. This paper also presents a new critical race free STT state assignment which produces a simple form of design equations that greatly simplifies the ILA realizations.

Liu, M. N.↗
NASA NTRS2006

Design of a Multi-Level/Analog Ferroelectric Memory Device

Increasing the memory density and utilizing the dove1 characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used as a reference to determine the amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. It is predicted that each memory cell may be able to store 8 bits or more. The design is based on data taken from actual ferroelectric transistors. Although the circuit has not been fabricated, a prototype circuit is now under construction. The design of this circuit is different than multi-level FLASH or silicon transistor circuits. The differences between these types of circuits are described in this paper. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

MacLeod, Todd C.↗
NASA NTRS1994

Silicon device performance measurements to support temperature range enhancement

Silicon based power devices can be used at 200 C. The device measurements made during this program show a predictable shift in device parameters with increasing temperature. No catastrophic or abrupt changes occurred in the parameters over the temperature range. As expected, the most dramatic change was the increase in leakage currents with increasing temperature. At 200 C the leakage current was in the milliAmp range but was still several orders of magnitude lower than the on-state current capabilities of the devices under test. This increase must be considered in the design of circuits using power transistors at elevated temperature. Three circuit topologies have been prototyped using MOSFET's and IGBT's. The circuits were designed using zero current or zero voltage switching techniques to eliminate or minimize hard switching of the power transistors. These circuits have functioned properly over the temperature range. One thousand hour life data have been collected for two power supplies with no failures and no significant change in operating efficiency. While additional reliability testing should be conducted, the feasibility of designing soft switched circuits for operation at 200 C has been successfully demonstrated.

Bromstead, James↗
NASA NTRS1965

Transistor voltage comparator performs own sensing

Detection of the highest voltage input among a group of varying voltage inputs is accomplished by a transistorized voltage comparison circuit. The collector circuits of the transistors perform the sensing function. Input voltage levels are governed by the transistors.

Cliff, R. A.↗
NASA NTRS1974

Ultra-stable oscillator with complementary transistors

A high frequency oscillator, having both good short and long term stability, is formed by including a piezoelectric crystal in the base circuit of a first bi-polar transistor circuit, the bi-polar transistor itself operated below its transitional frequency and having its emitter load chosen so that the input impedance, looking into the base thereof, exhibits a negative resistance in parallel with a capacitive reactance. Combined with this basic circuit is an auxiliary, complementary, second bi-polar transistor circuit of the same form with the piezoelectric crystal being common to both circuits. By this configuration small changes in quiescent current are substantially cancelled by opposite variations in the second bi-polar transistor circuit, thereby achieving from the oscillator a signal having its frequency of oscillation stable over long time periods as well as short time periods.

Kleinberg, L. L.↗
NASA NTRS1974

High isolation RF signal selection switches

A selection switch with high isolation between RF signal input terminals is achieved with a gated Schmitt trigger circuit feeding into a control NAND gate in each signal switching channel. The control NAND gates of the separate signal channels are coupled to an output terminal by a single NAND gate. The schmitt trigger circuits and all gates are implemented with Schottky transistor-transistor logic circuits having input clamping diodes. Each Schmitt trigger circuit includes two cascaded NAND gates and a feedback isolation Schottky diode between one input terminal connected to receive an RF input and another input terminal connected to receive a feedback signal from the second of the two cascaded NAND gates. Both NAND gates of the Schmitt trigger circuits are enabled by the same switch control signal which enables the control gates.

Hanna, M. F.↗
NASA NTRS2007

G4-FETs as Universal and Programmable Logic Gates

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Johnson, Travis↗
NASA NTRS1973

Gyrator employing field effect transistors

A gyrator circuit of the conventional configuration of two amplifiers in a circular loop, one producing zero phase shift and the other producing 180 deg phase reversal is examined. All active elements are MOS field effect transistors. Each amplifier comprises a differential amplifier configuration with current limiting transistor, followed by an output transistor in cascode configuration, and two load transistors of opposite conductivity type from the other transistors. A voltage divider control circuit comprises a series string of transistors with a central voltage input to provide control, with locations on the amplifiers receiving reference voltages by connection to appropriate points on the divider. The circuit produces excellent response and is well suited for fabrication by integrated circuits.

Hochmair, E. S.↗
NASA NTRS1964

Field effect transistors used as voltage controlled resistors

Two new methods of incorporating field effect transistors into circuit designs have resulted in linear response of this type transistor over a wide range of controlled voltage levels. This increases its usefulness as a voltage-controlled resistor.

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