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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
NASA NTRS1976

Design, processing, and testing of LSI arrays for space station

The applicability of a particular process for the fabrication of large scale integrated circuits is described. Test arrays were designed, built, and tested, and then utilized. A set of optimum dimensions for LSI arrays was generated. The arrays were applied to yield improvement through process innovation, and additional applications were suggested in the areas of yield prediction, yield modeling, and process reliability.

Ipri, A. C.↗
NASA NTRS1990

Forward Bias Inhibits Single-Event Upsets

Bipolar integrated circuits more resistant to ionizing radiation. Tests show resistance of bipolar integrated logic or memory circuit by single-event upsets increased by imparting forward bias to diode constituted by buried layer of substrate and collector.

Zoutendyk, John A.↗
NASA NTRS1989

Universal test fixture for monolithic mm-wave integrated circuits calibrated with an augmented TRD algorithm

The design and evaluation of a novel fixturing technique for characterizing millimeter wave solid state devices is presented. The technique utilizes a cosine-tapered ridge guide fixture and a one-tier de-embedding procedure to produce accurate and repeatable device level data. Advanced features of this technique include nondestructive testing, full waveguide bandwidth operation, universality of application, and rapid, yet repeatable, chip-level characterization. In addition, only one set of calibration standards is required regardless of the device geometry.

Romanofsky, Robert R.↗
NASA NTRS2021

The Use of High Energy Heavy Ion Facilities for Single Event Effects (SEE) Testing: A Perspective on Return on Investment (ROI)

With challenges related to testing highly complex integrated circuits as well as entire systems continuing to grow, the use of higher energy heavy ions for single-event effects (SEE) testing becomes a critical technical need. This presentation, however, focuses only partially on the technical side with the main emphasis on the economics of using a high-energy heavy ion beam and comparing via notional cost models for testing.

Kenneth A. LaBel↗
NASA NTRS1976

Implementation of Large Scale Integrated (LSI) circuit design software

Portions of the Computer Aided Design and Test system, a collection of Large Scale Integrated (LSI) circuit design programs were modified and upgraded. Major modifications were made to the Mask Analysis Program in the form of additional operating commands and file processing options. Modifications were also made to the Artwork Interactive Design System to correct some deficiencies in the original program as well as to add several new command features related to improving the response of AIDS when dealing with large files. The remaining work was concerned with updating various programs within CADAT to incorporate the silicon on sapphire silicon gate technology.

Kuehlthau, R. L.↗
NASA NTRS2004

Mitigation of High Altitude and Low Earth Orbit Radiation Effects on Microelectronics via Shielding or Error Detection and Correction Systems

The NASA Cooperative Agreement NAG4-210 was granted under the FY2000 Faculty Awards for Research (FAR) Program. The project was proposed to examine the effects of charged particles and neutrons on selected random access memory (RAM) technologies. The concept of the project was to add to the current knowledge of Single Event Effects (SEE) concerning RAM and explore the impact of selected forms of radiation on Error Detection and Correction Systems. The project was established as an extension of a previous FAR awarded to Prairie View A&M University (PVAMU), under the direction of Dr. Richard Wilkins as principal investigator. The NASA sponsored Center for Applied Radiation Research (CARR) at PVAMU developed an electronic test-bed to explore and quantify SEE on RAM from charged particles and neutrons. The test-bed was developed using 486DX microprocessor technology (PC-104) and a custom test board to mount RAM integrated circuits or other electronic devices. The test-bed had two configurations - a bench test version for laboratory experiments and a 400 Hz powered rack version for flight experiments. The objectives of this project were to: 1) Upgrade the Electronic Test-bed (ETB) to a Pentium configuration; 2) Accommodate more than only 8 Mbytes of RAM; 3) Explore Error Detection and Correction Systems for radiation effects; 4) Test modern RAM technologies in radiation environments.

Gupta, Kajal↗
NASA NTRS1990

Design of an optically controlled Ka-band GaAs MMIC phased-array antenna

Phased array antennas long were investigated to support the agile, multibeam radiating apertures with rapid reconfigurability needs of radar and communications. With the development of the Monolithic Microwave Integrated Circuit (MMIC), phased array antennas having the stated characteristics are becoming realizable. However, at K-band frequencies (20 to 40 GHz) and higher, the problem of controlling the MMICs using conventional techniques either severely limits the array size or becomes insurmountable due to the close spacing of the radiating elements necessary to achieve the desired antenna performance. Investigations were made that indicate using fiber optics as a transmission line for control information for the MMICs provides a potential solution. By adding an optical interface circuit to pre-existing MMIC designs, it is possible to take advantage of the small size, lightweight, mechanical flexibility and RFI/EMI resistant characteristics of fiber optics to distribute MMIC control signals. The architecture, circuit development, testing and integration of optically controlled K-band MMIC phased array antennas are described.

Kunath, Richard R.↗
NASA NTRS1990

Design of an optically controlled Ka-band GaAs MMIC phased-array antenna

Phased array antennas long were investigated to support the agile, multibeam radiating apertures with rapid reconfigurability needs of radar and communications. With the development of the Monolithic Microwave Integrated Circuit (MMIC), phased array antennas having the stated characteristics are becoming realizable. However, at K-band frequencies (20 to 40 GHz) and higher, the problem of controlling the MMICs using conventional techniques either severely limits the array size or becomes insurmountable due to the close spacing of the radiating elements necessary to achieve the desired antenna performance. Investigations were made that indicate using fiber optics as a transmission line for control information for the MMICs provides a potential solution. By adding an optical interface circuit to pre-existing MMIC designs, it is possible to take advantage of the small size, lightweight, mechanical flexibility and RFI/EMI resistant characteristics of fiber optics to distribute MMIC control signals. The architecture, circuit development, testing and integration of optically controlled K-band MMIC phased array antennas are described.

Kunath, Richard R.↗
NASA NTRS1979

Quality control during IC processing

Manual gives detailed test procedures for controlling silicon-wafer processing in manufacture of integrated circuits. Included among 43 test procedures are: ionic, bacterial, and solids contamination of high-purity water needed for wafer processing; crystallographic reflection, purity, and orientation; substrate dimensions and finish; thickness of deposited epitaxial films; oxide quality; photoresist characteristics; pinholes in insulating layers; metallized adhesion; and quality of ohmic contact.

Source record↗
NASA NTRS2004

A Re-programmable Platform for Dynamic Burn-in Test of Xilinx Virtexll 3000 FPGA for Military and Aerospace Applications

Field Programmable Gate Arrays (FPGA) have played increasingly important roles in military and aerospace applications. Xilinx SRAM-based FPGAs have been extensively used in commercial applications. They have been used less frequently in space flight applications due to their susceptibility to single-event upsets. Reliability of these devices in space applications is a concern that has not been addressed. The objective of this project is to design a fully programmable hardware/software platform that allows (but is not limited to) comprehensive static/dynamic burn-in test of Virtex-II 3000 FPGAs, at speed test and SEU test. Conventional methods test very few discrete AC parameters (primarily switching) of a given integrated circuit. This approach will test any possible configuration of the FPGA and any associated performance parameters. It allows complete or partial re-programming of the FPGA and verification of the program by using read back followed by dynamic test. Designers have full control over which functional elements of the FPGA to stress. They can completely simulate all possible types of configurations/functions. Another benefit of this platform is that it allows collecting information on elevation of the junction temperature as a function of gate utilization, operating frequency and functionality. A software tool has been implemented to demonstrate the various features of the system. The software consists of three major parts: the parallel interface driver, main system procedure and a graphical user interface (GUI).

Field Programmable Gate Arrays (FPGA)↗
NASA NTRS1982

Water-Vapor Sample Holder for Mass Spectrometers

Water-vapor sample holder for mass spectrometer contains water vapor for calibration. It is sealed by aluminum disk. Calibration sample and integrated circuit modules are tested sequentially in same manner.

Haack, R. F.↗
NASA NTRS1991

Test Adapter For Infrared Detectors

Convenient fixture for testing infrared detector integrated circuits, such as those used in surveying sensors, optical communications, receivers, optical power meters, and noncontacting thermometers. Includes electrical connections for 42-pin dual-in-line package (DIP), thermal connection to cryogenic probe, and optical filter. Using fixture, electrical and optical properties of detector measured at 4 K.

Campbell, Albert G.↗
NASA NTRS1992

Laser Scanner Tests For Single-Event Upsets

Microelectronic advanced laser scanner (MEALS) is opto/electro/mechanical apparatus for nondestructive testing of integrated memory circuits, logic circuits, and other microelectronic devices. Multipurpose diagnostic system used to determine ultrafast time response, leakage, latchup, and electrical overstress. Used to simulate some of effects of heavy ions accelerated to high energies to determine susceptibility of digital device to single-event upsets.

Kim, Quiesup↗
NASA NTRS2006

Stainless Steel NaK Circuit Integration and Fill Submission

The Early Flight Fission Test Facilities (EFF-TF) team has been tasked by the Marshall Space Flight Center Nuclear Systems Office to design, fabricate, and test an actively pumped alkali metal flow circuit. The system, which was originally designed to hold a eutectic mixture of sodium potassium (NaK), was redesigned to hold lithium; but due to a shift in focus, it is once again being prepared for use with NaK. Changes made to the actively pumped, high temperature loop include the replacement of the expansion reservoir, addition of remotely operated valves, and modification of the support table. Basic circuit components include: reactor segment, NaK to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and a spill reservoir. A 37-pin partial-array core (pin and flow path dimensions are the same as those in a full design) was selected for fabrication and test. This document summarizes the integration and fill of the pumped liquid metal NaK flow circuit.

Garber, Anne E.↗
NASA NTRS2025

System for Long-Duration Electrical Testing of SiC IC Generation 12 Chips at 500 °C

The system described in this report is an improved testing rig designed to enhance measurement flexibility, provide a compact oven footprint, and reduce costs for parallel oven-testing silicon carbide (SiC) integrated circuit devices at 500 °C for long durations (greater than 100 h). The testing rig design was characterized in terms of the ovens’ internal and external temperatures, system noise, and the leakage properties of their substrate/inner boards, where the devices under test (DUTs) reside. The test rig employs a National Instruments (NI) Peripheral Component Interconnect eXtensions for Instrumentation (PXI) measurement system, room-temperature pin-switching/customizing boards, and high-temperature compact ovens.

Stephanie Booth↗
NASA NTRS1998

Proton Damage Effects in Linear Integrated Circuts

Proton testing of linear circuits has identified devices where significantly more damage occurs at equivalent total dose levels with protons than tests with gamma rays.

lateral pnp transistors proton damage effects line↗