Search NASA⌕ Search

SEARCH · Search NASA

Results for “input device”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 1,027 records · Page 57
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Roles of temperature, materials, and domain inversion in high-performance, low-bias-drift thin film lithium niobate blue light modulators

We demonstrate a thin film lithium niobate electro-optic modulator operating at 456 nm with an RF voltage-length product of 0.38 V-cm and a bandwidth of 6.9 GHz. We test the dielectric relaxation of the modulator with sweeps of temperature and optical input power, and compare equivalent modulators with electrode materials of Cr-Au, Ti-Au and Al in terms of bias stability and current-voltage characteristics. We demonstrate bias stability over at least 8 hours with Al devices, and show relationships between drift, I-V characteristics and ferroelectric domain switching.

Celik, Oguz Tolga (ORCID:0000000264542306)↗
NASA NTRS1973

Lamp pumped Nd:YAG laser. Space-qualifiable Nd:YAG laser for optical communications

Results are given of a program concerned with the design, fabrication, and evaluation of alkali pump lamps for eventual use in a space qualified Nd:YAG laser system. The study included evaluation of 2mm through 6mm bore devices. Primary emphasis was placed upon the optimization of the 4mm bore lamp and later on the 6mm bore lamp. As part of this effort, reference was made to the Sylvania work concerned with the theoretical modeling of the Nd:YAG laser. With the knowledge gained, a projection of laser performance was made based upon realistic lamp parameters which should easily be achieved during following developmental efforts. Measurements were made on the lamp performance both in and out of the cavity configuration. One significant observation was that for a constant vapor pressure device, the spectral and fluorescent output did not vary for vacuum or argon environment. Therefore, the laser can be operated in an inert environment (eg. argon) with no degradation in output. Laser output of 3.26 watts at 430 watts input was obtained for an optimized 4mm bore lamp.

Ward, K. B.↗
NASA NTRS1981

The monogroove high performance heat pipe

The development of the monogroove heat pipe, a fundamentally new high-performance device suitable for multi-kilowatt space radiator heat-rejection systems, is reported. The design separates heat transport and transfer functions, so that each can be separately optimized to yield heat transport capacities on the order of 25 kW/m. Test versions of the device have proven the concept of heat transport capacity control by pore dimensions and the permeability of the circumferential wall wick structure, which together render it insensitive to tilt. All cases tested were for localized, top-side heat input and cooling and produced results close to theoretical predictions.

Alario, J.↗
NASA NTRS1995

Improved Solid-State Microanemometer

Improved solid-state microanemometer suitable for measuring flows in variety of biomedical, industrial, and other applications. Small size, unique design, and one-piece construction provides combination of short response time, structural rigidity, optimal dissipation of heat, and versatility in application. Device includes four integral sensing resistors exposed to flow measured and serves as hot-film anemometer subunits. Sensing resistors connected to external excitation-and-measurement circuits operating in any of standard hot-film-anemometer modes; constant input voltage, constant input current, or constant resistance with feedback.

Henderson, H. Thurman↗
DOE OSTI2020

Integrated circuits with programmable gate timing signal generation for power converters and apparatus comprising the same

An apparatus is disclosed that includes a semiconductor device to control a power converter having two or more power FETs. The semiconductor device includes a gate signal generator configured to produce two or more gate signals able to drive the two or more FETs. The gate signal generator has programmable timing configuration parameters to control operation of the two or more gate signals, wherein the timing configuration parameters are digitally programmed via a memory in the semiconductor device. The memory may be implemented with fuses, other non-volatile memory or volatile memory. The parameters may be fixed or updated during a lifetime of the apparatus. A serial-to-parallel conversion may be used to input the parameters. Optimization methods may be performed to determine parameters considered to be optimal. The apparatus may also include the power converter.

42 ENGINEERING↗
NASA NTRS1978

Time-delay-and-integration charge-coupled devices using tin oxide gate technology

Doped tin oxide gates are used in a time-delay-and-integration (TDI) CCD scheme in an effort to develop a stable transparent gate technology. Design characteristics of the system are discussed, including 2 sections of 10 by 9 integration stages, four-phase buried channel construction, and 10 input parallel-in/serial-out output shift register at a video rate of 1.25 MHz. A quantum efficiency of 65% with smooth spectral response is attained by front surface imaging. The suitability of the system for the Landsat program is discussed in terms of TDI-CCD operating parameters.

Thompson, L. L.↗
NASA NTRS2013

FPGA Flash Memory High Speed Data Acquisition

The purpose of this research is to design and implement a VHDL ONFI Controller module for a Modular Instrumentation System. The goal of the Modular Instrumentation System will be to have a low power device that will store data and send the data at a low speed to a processor. The benefit of such a system will give an advantage over other purchased binary IP due to the capability of allowing NASA to re-use and modify the memory controller module. To accomplish the performance criteria of a low power system, an in house auxiliary board (Flash/ADC board), FPGA development kit, debug board, and modular instrumentation board will be jointly used for the data acquisition. The Flash/ADC board contains four, 1 MSPS, input channel signals and an Open NAND Flash memory module with an analog to digital converter. The ADC, data bits, and control line signals from the board are sent to an Microsemi/Actel FPGA development kit for VHDL programming of the flash memory WRITE, READ, READ STATUS, ERASE, and RESET operation waveforms using Libero software. The debug board will be used for verification of the analog input signal and be able to communicate via serial interface with the module instrumentation. The scope of the new controller module was to find and develop an ONFI controller with the debug board layout designed and completed for manufacture. Successful flash memory operation waveform test routines were completed, simulated, and tested to work on the FPGA board. Through connection of the Flash/ADC board with the FPGA, it was found that the device specifications were not being meet with Vdd reaching half of its voltage. Further testing showed that it was the manufactured Flash/ADC board that contained a misalignment with the ONFI memory module traces. The errors proved to be too great to fix in the time limit set for the project.

Gonzalez, April↗
DOE OSTI2024

Collective dynamics and long-range order in thermal neuristor networks

Abstract In the pursuit of scalable and energy-efficient neuromorphic devices, recent research has unveiled a novel category of spiking oscillators, termed “thermal neuristors.” These devices function via thermal interactions among neighboring vanadium dioxide resistive memories, emulating biological neuronal behavior. Here, we show that the collective dynamical behavior of networks of these neurons showcases a rich phase structure, tunable by adjusting the thermal coupling and input voltage. Notably, we identify phases exhibiting long-range order that, however, does not arise from criticality, but rather from the time non-local response of the system. In addition, we show that these thermal neuristor arrays achieve high accuracy in image recognition and time series prediction through reservoir computing, without leveraging long-range order. Our findings highlight a crucial aspect of neuromorphic computing with possible implications on the functioning of the brain: criticality may not be necessary for the efficient performance of neuromorphic systems in certain computational tasks.

Science & Technology - Other Topics↗
DOE OSTI2025

Characterizing and Modeling the Influence of Geometry on the Performance of Superconducting Nanowire Cryotrons

The scaling of superconducting nanowire detectors to larger arrays is often limited by room-temperature-readout cabling. Cryogenic integrated circuits constructed from nanowire cryotrons, or nanocryotrons, can address this limitation by performing signal processing on chip. In this study, we characterize key performance metrics of the nanocryotron to elucidate its potential as a logical element in cryogenic integrated circuits and develop an electro-thermal model to connect material parameters with device performance. We find that the performance of the nanocryotron depends on the device geometry, and trade-offs are associated with optimizing the gain, jitter, and energy dissipation. Here, we demonstrate that nanocryotrons fabricated on niobium nitride can achieve a grey zone less than 210 nA wide for a 5 ns long input pulse corresponding to a maximum achievable gain of 48 dB, an energy dissipation of less than 20 aJ per operation, and a jitter of less than 60 ps.

Superconductor↗
DOE OSTI2023

Efficient human activity recognition with spatio-temporal spiking neural networks

In this study, we explore Human Activity Recognition (HAR), a task that aims to predict individuals' daily activities utilizing time series data obtained from wearable sensors for health-related applications. Although recent research has predominantly employed end-to-end Artificial Neural Networks (ANNs) for feature extraction and classification in HAR, these approaches impose a substantial computational load on wearable devices and exhibit limitations in temporal feature extraction due to their activation functions. To address these challenges, we propose the application of Spiking Neural Networks (SNNs), an architecture inspired by the characteristics of biological neurons, to HAR tasks. SNNs accumulate input activation as presynaptic potential charges and generate a binary spike upon surpassing a predetermined threshold. This unique property facilitates spatio-temporal feature extraction and confers the advantage of low-power computation attributable to binary spikes. We conduct rigorous experiments on three distinct HAR datasets using SNNs, demonstrating that our approach attains competitive or superior performance relative to ANNs, while concurrently reducing energy consumption by up to 94%.

60 APPLIED LIFE SCIENCES↗
NASA NTRS1996

X-Ray Diffraction Apparatus

An x-ray diffraction apparatus for use in analyzing the x-ray diffraction pattern of a sample is introduced. The apparatus includes a beam source for generating a collimated x-ray beam having one or more discrete x-ray energies, a holder for holding the sample to be analyzed in the path of the beam, and a charge-coupled device having an array of pixels for detecting, in one or more selected photon energy ranges, x-ray diffraction photons produced by irradiating such a sample with said beam. The CCD is coupled to an output unit which receives input information relating to the energies of photons striking each pixel in the CCD, and constructs the diffraction pattern of photons within a selected energy range striking the CCD.

Blake, David F.↗
NASA NTRS2008

Radiation-Insensitive Inverse Majority Gates

To help satisfy a need for high-density logic circuits insensitive to radiation, it has been proposed to realize inverse majority gates as microscopic vacuum electronic devices. In comparison with solid-state electronic devices ordinarily used in logic circuits, vacuum electronic devices are inherently much less adversely affected by radiation and extreme temperatures. The proposed development would involve state-of-the-art micromachining and recent advances in the fabrication of carbon-nanotube-based field emitters. A representative three-input inverse majority gate would be a monolithic, integrated structure that would include three gate electrodes, six bundles of carbon nanotubes (serving as electron emitters) at suitable positions between the gate electrodes, and an overhanging anode. The bundles of carbon nanotubes would be grown on degenerately doped silicon substrates that would be parts of the monolithic structure. The gate electrodes would be fabricated as parts of the monolithic structure by means of a double-silicon-on-insulator process developed at NASA's Jet Propulsion Laboratory. The tops of the bundles of carbon nanotubes would lie below the plane of the tops of the gate electrodes. The particular choice of shapes, dimensions, and relative positions of the electrodes and bundles of carbon nanotubes would provide for both field emission of electrons from the bundles of carbon nanotubes and control of the electron current to obtain the inverse majority function, which is described in the paper.

Manohara, Harish↗
NASA NTRS2011

Source-Coupled, N-Channel, JFET-Based Digital Logic Gate Structure Using Resistive Level Shifters

A circuit topography is used to create usable, digital logic gates using N (negatively doped) channel junction field effect transistors (JFETs), load resistors, level shifting resistors, and supply rails whose values are based on the DC parametric distributions of these JFETs. This method has direct application to the current state-of-the-art in high-temperature (300 to 500 C and higher) silicon carbide (SiC) device production, and defines an adaptation to the logic gate described in U.S. Patent 7,688,117 in that, by removing the level shifter from the output of the gate structure described in the patent (and applying it to the input of the same gate), a source-coupled gate topography is created. This structure allows for the construction AND/OR (sum of products) arrays that use far fewer transistors and resistors than the same array as constructed from the gates described in the aforementioned patent. This plays a central role when large multiplexer constructs are necessary; for example, as in the construction of memory. This innovation moves the resistive level shifter from the output of the basic gate structure to the front as if the input is now configured as what would be the output of the preceding gate, wherein the output is the two level shifting resistors. The output of this innovation can now be realized as the lone follower transistor with its source node as the gate output. Additionally, one may leave intact the resistive level shifter on the new gate topography. A source-coupled to direct-coupled logic translator will be the result.

Krasowski, Michael J.↗
NASA NTRS2003

Curved Focal-Plane Arrays Using Back-Illuminated High-Purity Photodetectors

Curved-focal-plane arrays of back-illuminated silicon-based photodetectors are being developed. The basic idea is to improve the performance of an imaging instrument and simplify the optics needed to obtain a given level of performance by making an image sensor (e.g., a photographic film or an array of photodetectors) conform to a curved focal surface, instead of following the customary practice of designing the optics to project an image onto a flat focal surface. Eyes are natural examples of optical systems that have curved focal surfaces on which image sensors (retinas) are located. One prior approach to implementation of this concept involves the use of curved-input-surface microchannel plates as arrays of photodetectors. In comparison with microchannel plates, these curved-focal-plane arrays would weigh less, operate at much lower voltages, and consume less power. It should also be possible to fabricate the proposed devices at lower cost. It would be possible to fabricate an array of photodetectors and readout circuitry in the form of a very-large-scale integrated (VLSI) circuit on a curved focal surface, but it would be difficult and expensive to do so. In a simple and inexpensive alternate approach, a device (see figure) would have (1) a curved back surface, onto which light would be focused; and (2) a flat front surface, on which VLSI circuitry would be fabricated by techniques that are well established for flat surfaces. The device would be made from ultrapure silicon, in which it is possible to form high-resistivity, thick photodetectors that are fully depleted through their thicknesses. (As used here, "thick means having a thickness between a fraction of a millimeter and a few millimeters.) The back surface would be polished to the curvature of the focal surface of the intended application. To enable the collection of charge carriers excited by photons near the back surface or in the bulk of the device, it would be necessary to form a transparent or semitransparent back-surface electrode, possibly by delta doping. [Delta doping is so named because its density-vs.-depth characteristic is reminiscent of the Dirac function (impulse function): the dopant is concentrated in a very thin layer - nominally, a single atomic layer.]

Nikzad, Shouleh↗
NASA NTRS2015

Multistage Force Amplification of Piezoelectric Stacks

Embodiments of the disclosure include an apparatus and methods for using a piezoelectric device, that includes an outer flextensional casing, a first cell and a last cell serially coupled to each other and coupled to the outer flextensional casing such that each cell having a flextensional cell structure and each cell receives an input force and provides an output force that is amplified based on the input force. The apparatus further includes a piezoelectric stack coupled to each cell such that the piezoelectric stack of each cell provides piezoelectric energy based on the output force for each cell. Further, the last cell receives an input force that is the output force from the first cell and the last cell provides an output apparatus force In addition, the piezoelectric energy harvested is based on the output apparatus force. Moreover, the apparatus provides displacement based on the output apparatus force.

Xu, Tian-Bing↗
DOE OSTI2023

Soft error-mitigating semiconductor design system and associated methods

A soft error-mitigating semiconductor design system and associated methods that tailor circuit design steps to mitigate corruption of data in storage elements (e.g., flip flops) due to Single Events Effects (SEEs). Required storage elements are automatically mapped to triplicated redundant nodes controlled by a voting element that enforces majority-voting logic for fault-free output (i.e., Triple Modular Redundancy (TMR)). Storage elements are also optimally positioned for placement in keeping with SEE-tolerant spacing constraints. Additionally, clock delay insertion (employing either a single global clock or clock triplication) in the TMR specification may introduce useful skew that protects against glitch propagation through the designed device. The resultant layout generated from the TMR configuration may relax constraints imposed on register transfer level (RTL) engineers to make rad-hard designs, as automation introduces TMR storage registers, memory element spacing, and clock delay/triplication with minimal designer input.

Miryala, Sandeep↗
DOE OSTI2024

High Performance Heat Pipe Power Transient Testing at SPHERE Facility

Microreactors are being researched, designed, and built at Idaho National Laboratory (INL). Microreactors are small reactors defined at less than 20MW of power. These reactor concepts are also being looked at throughout industry for various applications. An important aspect of these reactor designs is economic feasibility i.e. lower overnight capital cost. The driving factors for implementing microreactors are quick setup and takedown, minimal operators, and the ability to manufacture them readily and to fit in mid-sized containers for transport. A specific area of research to aid in successful integration of these factors within the designs is passive heat removal of the core’s thermal power. Interest in heat pipes to achieve this passive heat removal has been shown across multiple industry partners. Because of this interest, INL has developed a test facility to facilitate experimental tests for sodium filled heat pipes. INL has developed the Single Primary Heat Extraction and Removal Emulator (SPHERE) facility to run experiments on high performance, sodium filled heat pipes. As mentioned above, heat pipes are passive heat transfer devices. Radially, heat pipes are broken up into an outer wall, a small annular gap, a wick structure, and a centerline gap. They function by utilizing latent heat transfer. Heat pipes are traditionally separated into three regions, an evaporator (heat input), an adiabatic region, and finally a condenser region (heat removal). As heat is being applied to the evaporator, the working fluid undergoes a phase change to a vapor. This phase change causes a differential pressure across the axial length of the pipe driving flow down the center gap of the heat pipe. The vapor flows down past the adiabatic region to the condenser where the heat is removed. This heat removal forces the working fluid to phase change back to a liquid. The wick structure is then utilized to drive the flow back towards the evaporator by capillary forces. This backflow is aided by the annular gap. Because this heat transfer mechanism functions with latent heat transfer, the heat pipe is close to isothermal down the axial length. Heat pipes can operate under a wide range of working fluids. Considerations for these working fluids are primarily driven by operating temperatures amongst other important factors based around overall performance. Sodium filled heat pipes operate from 450°C up to 900°C. This temperature range works well for the current microreactor designs. In conjunction with this experimental capability, INL has developed a modeling software to simulate heat pipe physics within reactor cores. This modeling software is called Sockeye and functions under the established INL Multiphysics Object Oriented Simulation Environment (MOOSE). SPHERE also supports Sockeye development by providing the modeling team with experimental data on an array of setups and operating parameters to support validation efforts. A power transient experiment was performed utilizing the SPHERE facility to continue to aid with Sockeye development. The testing followed a proposed test plan to ramp up and down the temperature of the heat pipe. Sockeye models steady state heat pipe operation with high accuracy, the data provided by the power transient testing aims to assist with the validation efforts and further enhance transient modeling capability of the tool [2].

22 GENERAL STUDIES OF NUCLEAR REACTORS↗
DOE OSTI2024

Additive manufacturing system with at least one electronic nose

An additive manufacturing system comprising at least one electronic nose (e-nose) is provided. The e-nose may comprise a housing and gas sensors. The housing may have an air channel. The active sensor portion of the sensors are positioned in the air channel. The housing may be mounted to an extruder head of an additive manufacturing device. The system may also comprise a processor. The processor may determine whether there is an abnormality in an additive manufacturing process based on one or more combinations of outputs from the gas sensors received during the additive manufacturing process input into a deployed machine learning model; and generate a report for the additive manufacturing process containing the determination.

Ivanov, Ilia N.↗