Search NASA⌕ Search

SEARCH · Search NASA

Results for “MOS transistor”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 109 records · Page 6
All sourcesNASA NTRSDOE OSTI
NASA NTRS2008

Efficient G(sup 4)FET-Based Logic Circuits

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

Vatan, Farrokh↗
NASA NTRS1984

Si MOS devices at low temperatures

Low temperature operation of micron and submicron size Si MOSFETs (metal-oxide-semiconductor field-effect-transistors) results in their improved device characteristics. Various low temperature device properties such as increase in mobility, shift in the theshold voltage, increased reliability, etc., were considered. Other device characteristics such as the subthreshold behavior, delay times and miniaturization at low temperatures are discussed. Discussion includes presenting experimental results along with physical models explaining the observed effects.

Kamgar, A.↗
NASA NTRS2009

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

Phillips, Thomas A.↗
NASA NTRS1998

Proton Damage Effects in Linear Integrated Circuts

Proton testing of linear circuits has identified devices where significantly more damage occurs at equivalent total dose levels with protons than tests with gamma rays.

lateral pnp transistors proton damage effects line↗
DOE OSTI2020

Spatial defects nanoengineering for bipolar conductivity in MoS 2

Understanding the atomistic origin of defects in two-dimensional transition metal dichalcogenides, their impact on the electronic properties, and how to control them is critical for future electronics and optoelectronics. Here, we demonstrate the integration of thermochemical scanning probe lithography (tc-SPL) with a flow-through reactive gas cell to achieve nanoscale control of defects in monolayer MoS 2 . The tc-SPL produced defects can present either p- or n-type doping on demand, depending on the used gasses, allowing the realization of field effect transistors, and p-n junctions with precise sub-μm spatial control, and a rectification ratio of over 10 4 . Doping and defects formation are elucidated by means of X-Ray photoelectron spectroscopy, scanning transmission electron microscopy, and density functional theory. We find that p-type doping in HCl/H 2 O atmosphere is related to the rearrangement of sulfur atoms, and the formation of protruding covalent S-S bonds on the surface. Alternatively, local heating MoS 2 in N 2 produces n-character.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Focused Helium Ion Beam for Direct Patterning of Monolayer MoS 2 Nanoribbon Field Effect Devices

The helium ion microscope (HIM) focused ion beam (FIB) has emerged as a powerful tool to directly pattern nanostructures below 10 nm due to its high-resolution capabilities and the inert nature of the ion source. These attributes make HIM FIB particularly interesting for patterning 2D materials such as transition metal dichalcogenides (TMDs) to investigate transport phenomena at the nanoscale. Reported here is the fabrication of MoS 2 nanoribbon devices using HIM FIB-induced etching (FIBIE) with XeF 2 , allowing for reduced ion dose compared to direct sputtering. While patterning is efficacious, the devices exhibit performance degradation with decreasing nanoribbon width due to damage up to 150 nm beyond the patterned edge. Incorporating an hBN encapsulation improves device performance by one order of magnitude, although the lateral extent of damage remains unchanged. The spatial distribution of damage is shown to be determined by the forward- and backscattered ions and electrons, while the hBN encapsulation layer substantially reduces damage from XeF 2 interactions in unexposed regions. Raman and photoluminescence (PL) measurements corroborate these findings, while ion/solid interaction simulations further elucidate the resolution limits imposed by substrate interactions. In conclusion, this work provides critical insights and a practical pathway for utilizing HIM FIBIE in 2D TMD functional device patterning.

MoS 2↗
NASA NTRS1979

Studies of silicon p-n junction solar cells

To provide theoretical support for investigating different ways to obtain high open-circuit voltages in p-n junction silicon solar cells, an analytical treatment of heavily doped transparent-emitter devices is presented that includes the effects of bandgap narrowing, Fermi-Dirac statistics, a doping concentration gradient, and a finite surface recombination velocity at the emitter surface. Topics covered include: (1) experimental determination of bandgap narrowing in the emitter of silicon p-n junction devices; (2) heavily doped transparent regions in junction solar cells, diodes, and transistors; (3) high-low-emitter solar cell; (4) determination of lifetimes and recombination currents in p-n junction solar cells; (5) MOS and oxide-charged-induced BSF solar cells; and (6) design of high efficiency solar cells for space and terrestrial applications.

Neugroschel, A.↗
NASA NTRS1985

MOS integrated circuit fault modeling

Three digital simulation techniques for MOS integrated circuit faults were examined. These techniques embody a hierarchy of complexity bracketing the range of simulation levels. The digital approaches are: transistor-level, connector-switch-attenuator level, and gate level. The advantages and disadvantages are discussed. Failure characteristics are also described.

Sievers, M.↗
NASA NTRS1993

Fault handling schemes in electronic systems with specific application to radiation tolerance and VLSI design

Naturally occurring space radiation particles can produce transient and permanent changes in the electrical properties of electronic devices and systems. In this work, the transient radiation effects on DRAM and CMOS SRAM were considered. In addition, the effect of total ionizing dose radiation of the switching times of CMOS logic gates were investigated. Effects of transient radiation on the column and cell of MOS dynamic memory cell was simulated using SPICE. It was found that the critical charge of the bitline was higher than that of the cell. In addition, the critical charge of the combined cell-bitline was found to be dependent on the gate voltage of the access transistor. In addition, the effect of total ionizing dose radiation on the switching times of CMOS logic gate was obtained. The results of this work indicate that, the rise time of CMOS logic gates increases, while the fall time decreases with an increase in total ionizing dose radiation. Also, by increasing the size of the P-channel transistor with respect to that of the N-channel transistor, the propagation delay of CMOS logic gate can be made to decrease with, or be independent of an increase in total ionizing dose radiation. Furthermore, a method was developed for replacing polysilicon feedback resistance of SRAMs with a switched capacitor network. A switched capacitor SRAM was implemented using MOS Technology. The critical change of the switched capacitor SRAM has a very large critical charge. The results of this work indicate that switched capacitor SRAM is a viable alternative to SRAM with polysilicon feedback resistance.

Attia, John Okyere↗
DOE OSTI2023

Nanoscale Ferroelectric Control of Novel Electronic States in Layered Two-Dimensional Materials (Final Report)

In this DOE Early Career project “Nanoscale Ferroelectric Control of Novel Electronic States in Layered Two-Dimensional Materials,” the PI’s group has combined ferroelectric field effect with nanoscale domain imaging and writing to design the electronic and optical properties of two-dimensional (2D) van der Waals materials, including graphene and transition metal dichalcogenides MoS2 and ReS2. The van der Waals materials have been prepared into field effect transistor (FET) devices with ferroelectric gates. Through domain patterning in a ferroelectric polymer PVDF-TrEF top-gate via conductive atomic force microscopy, the team has created programmable Schottky junctions in monolayer MoS 2 , where both barrier height and I-V rectifying polarity can be reconfigured. The transport anisotropy of monolayer to few-layer ReS 2 has been mapped out by defining the entire channel into an insulating state and creating nanoscale conducting paths along different directions through domain writing in the ferroelectric top-gate. The result shows that the conductivity along and perpendicular to the Re-chain can differ by >5.5x10 4 . Theoretical modeling points to the band origin of the transport anomaly and reveals the emergence of a flat band in few-layer ReS 2 . The interfacial epitaxial relation between ReS 2 and PVDF-TrFE further promotes the formation of close-packed, highly ordered PVDF-TrFE nanowires with width of 35 nm and 10 nm. Nonvolatile modulation of quantum Hall effect has been achieved in graphene FETs with a ferroelectric oxide Ba 0.4 Sr 0.6 TiO 3 back-gate. Scattering from the remote surface optical phonon in Ba 0.4 Sr 0.6 TiO 3 limits the room temperature mobility of graphene to be about 3x10 4 cm 2 /Vs. Steep-slope switching has been achieved in MoS 2 FETs back-gated by polycrystalline Pb(Zr,Ti)O 3 , which signals a static-state negative capacitance mode without involving an additional dielectric layer. Piezoresponse force microscopy studies show that the sub-threshold swing can be well correlated with the domain wall density in Pb(Zr,Ti)O 3 . The team also observes an unconventional filtering effect of the second harmonic generation response at the MoS 2 /Pb(Zr,Ti)O 3 heterointerface, which can be accounted for by the alignment between one of the polar axes of MoS 2 and the chiral dipole rotation at the surface of domain wall in Pb(Zr,Ti)O 3 . The research supported by this DOE grant has significantly advanced the fundamental understanding and functional design of ferroelectric/2D van der Waals heterostructures for their implementation towards energy applications.

36 MATERIALS SCIENCE↗
NASA NTRS1979

Radiation hardened PMOS process with ion implanted threshold adjust

By including specific process modifications the effect of ion implantation on radiation hardness can be minimized and radiation hard ion implanted MOS circuits can be fabricated. The experimental procedure followed was to examine key processing steps (with respect to radiation hardness) on ion-implanted individual PMOS transistors. The individual transistors were evaluated by continuously monitoring the threshold voltage as the transistors were being irradiated. By comparing runs it was possible to deduce what is considered a radiation hard ion implanted process. Tests with a complex LSI PMOS IC processor chip containing over 2000 transistors and resistors were also conducted

Jhabvala, M.↗
NASA NTRS1998

Multi-Dimensional Quantum Effect Simulation Using a Density-Gradient Model and Script-Level Programming Techniques

A density-gradient (DG) model is used to calculate quantum-mechanical corrections to classical carrier transport in MOS (Metal Oxide Semiconductor) inversion/accumulation layers. The model is compared to measured data and to a fully self-consistent coupled Schrodinger and Poisson equation (SCSP) solver. Good agreement is demonstrated for MOS capacitors with gate oxide as thin as 21 A. It is then applied to study carrier distribution in ultra short MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) with surface roughness. This work represents the first implementation of the DG formulation on multidimensional unstructured meshes. It was enabled by a powerful scripting approach which provides an easy-to-use and flexible framework for solving the fourth-order PDEs (Partial Differential Equation) of the DG model.

Rafferty, Connor S.↗
DOE OSTI2020

Insights into negative differential resistance in MoS 2 Esaki diodes: A first-principles perspective

MoS 2 is a two-dimensional material with a band gap depending on the number of layers and tunable by an external electric field. The experimentally observed intralayer band-to-band tunneling and interlayer band-to-band tunneling in this material present an opportunity for new electronic applications in tunnel field-effect transistors. However, such a widely accepted concept has yet to be been supported by theoretical investigations based on first principles. In this paper, using density functional theory, in conjunction with nonequilibrium Green's function techniques and our electric field gating method, enabled by a large-scale computational approach, we study the relation between band alignment and transmission in planar and side-stack MoS 2 p–i–n junction configurations. Here, we demonstrate the presence of negative differential resistance for both in-plane and interlayer current, a staple characteristic of tunnel diode junctions, and analyze the physical origin of such an effect. Electrostatic potentials, the van der Waals barrier, and a complex band analysis are also examined for a thorough understanding of Esaki diodes.

74 ATOMIC AND MOLECULAR PHYSICS↗
NASA NTRS1974

Integrated P-channel MOS gyrator

A gyrator circuit is described which is of the conventional configuration of two amplifiers in a circular loop, one producing zero phase shift and the other producing 180 phase reversal, in a circuit having medium Q composed of all field effect transistors of the same conductivity type. The current source to each gyrator amplifier comprises an amplifier which responds to changes in current, with the amplified signals feed back so as to limit current. The feedback amplifier has a large capacitor connected to bypass high frequency components, thereby stabilizing the output. The design makes possible fabrication of circuits with transistors of only one conductivity type, providing economies in manufacture and use.

Hochmair, E. S.↗
DOE OSTI2025

Phase transition in two-dimensional monolayer (1L)-molybdenum disulfide induced by atomic S-basal plane gliding via synchrotron X-ray monochromatic beam radiation for superior electronic performance

Here, in this work, we report a novel approach to reduce the channel resistance by inducing a phase transition behavior from 2H to 1T in a monolayer MoS 2 (1L-MoS 2 ) by a synchrotron X-ray monochromatic beam (mono-beam) radiation. The effects of the biphase structure by the mono-beam on the 1L-MoS2 film were investigated using Raman spectra, photoluminescence (PL) spectra, scanning tunneling microscopy, and scanning tunneling spectroscopy, respectively. Through material characterization, we identified that the lateral sliding of S-vacancies along the S-plane in the 1L-MoS 2 is the key reason for the origin of unidirectional phase transition. The precise phase engineering triggered by the mono-beam radiation process allows the realization of field-effect transistors (FET) with 2X improvement in mobility toward a high on/off ratio (~10 8 ) and a near-ideal subthreshold swing of ~88 mV per decade. The validity of the phase engineering could be further extended for its application as a memory device, exhibiting a gate tunable conduction modulation behavior and a high resistance ratio of ~10 2 at a gate bias of 5 V with endurance of ~100 cycles. Furthermore, an artificial neural network using the synaptic weight update with accuracy of ~93 % was achieved.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Unraveling the Mechanism of Interfacial Charge Transfer and Photoresponsivity of WS 2 Quantum Dots/MoS 2 (0D–2D) Heterostructure-Based Transistors

To assess the efficacy of a mixed-dimensional van der Waals (vdW) heterostructure in modulating the optoelectronic responses of nanodevices, the charge transport properties of the transition-metal dichalcogenide (TMD)-based heterostructure comprising zero-dimensional (0D) WS 2 quantum dots (QDs) and two-dimensional (2D) MoS 2 flakes are critically analyzed. Herein, a facile strategy was materialized in developing an atomically thin phototransistor assembled from mechanically exfoliated MoS 2 and WS 2 QDs synthesized using a one-pot hydrothermal route. The amalgamated photodetectors exhibited a high responsivity of ∼8000 A/W at an incident power of 0.05 nW of white light, surpassing that of the pristine MoS 2 devices. Furthermore, the detectivity of pristine MoS 2 , which was on the order of 10 10 , increased to 10 12 Jones for the WS 2 QDs/MoS 2 heterostructure photodetector, outperforming other WS 2 -based materials. The quasiparticle band gap and density of states (DOS) are further analyzed to elucidate the photophysics of the WS 2 QD/MoS 2 hybrid assembly. The difference in the work function between MoS 2 and WS 2 QDs gives rise to an electric field across the 0D–2D interface, facilitating effective charge separation and migration and contributing to the enhancement of photoresponsivity. The analysis of optical responses using density functional theory (DFT) revealed stronger absorption and less reflection over a broader spectrum of wavelengths for the heterostructure compared to the pristine materials. The estimated optical conductivity aligns well with the experimentally predicted maximum photoresponsivity under visible light, which is attributed to the high absorbance of 2D MoS 2 . In conclusion, combining diverse spectroscopic and imaging techniques with quantum simulation provides insights that clarify the pertinence of 0D–2D TMDs in designing phototransistors.

WS2 QDs/MoS2 heterostructure↗
DOE OSTI2024

FET Junction Temperature Monitoring Using Novel On-Chip Solution

A novel junction temperature monitoring sensor is proposed and experimentally demonstrated for application in MOS-gate power devices. The sensor is created using the polycide gate electrode layer of the devices to create a temperature-sensitive resistor without any additional fabrication steps. The resistor is located on the field oxide with one end grounded at the device reference terminal to isolate it from the device current and voltage transients. It allows in-situ monitoring of the device junction temperature during active circuit operation. The technology has been implemented to monitor the junction temperature of Silicon Carbide Junction Barrier Schottky Field Effect Transistors (SiC JBSFETs) with the bi-directional FET (BiDFET).

Bidirectional switches, SiC bidirectional FET, BiD↗