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Results for “single event upset”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 109 records · Page 6
All sourcesNASA NTRSDOE OSTI
NASA NTRS1981

Investigation for single-event upset in MSI devices

The reported investigation shows that low-power TTL, standard TTL, low-power Schottky, and Schottky devices are all subject to upset by heavy ions. Low-power Schottky was the most sensitive of the device technologies tested. No evidence was found to correlate sensitivity to cosmic rays with any particular device manufacturer. The probability of upset of the logic devices is comparable to that of RAM's on a per-flip-flop basis, based on RAM data obtained by Kolasinski et al. (1979). The testing was performed by subjecting the devices to 120 MeV krypton ions from a cyclotron.

Woods, J. P.↗
NASA NTRS1982

Single event upset vulnerability of selected 4K and 16K CMOS static RAM's

Upset thresholds for bulk CMOS and CMOS/SOS RAMS were deduced after bombardment of the devices with 140 MeV Kr, 160 MeV Ar, and 33 MeV O beams in a cyclotron. The trials were performed to test prototype devices intended for space applications, to relate feature size to the critical upset charge, and to check the validity of computer simulation models. The tests were run on 4 and 1 K memory cells with 6 transistors, in either hardened or unhardened configurations. The upset cross sections were calculated to determine the critical charge for upset from the soft errors observed in the irradiated cells. Computer simulations of the critical charge were found to deviate from the experimentally observed variation of the critical charge as the square of the feature size. Modeled values of series resistors decoupling the inverter pairs of memory cells showed that above some minimum resistance value a small increase in resistance produces a large increase in the critical charge, which the experimental data showed to be of questionable validity unless the value is made dependent on the maximum allowed read-write time.

Kolasinski, W. A.↗
NASA NTRS1984

The solar flare heavy ion environment for single-event upsets - A summary of observations over the last solar cycle, 1973-1983

A summary of observations of the flux of 25 to 400 MeV/nucleon heavy ions from solar flares is presented covering the period from late 1973 to early 1984. Distributions of flare occurrence frequency versus fluence, energy spectra, and composition are presented for the 30 events observed during this period, to quantify the variability of the heavy ion environment. A comparison of these data to a model environment suggests some refinements to the model. LET spectra based on the worst case flare observed are presented to illustrate the significance of the flare ion distribution and the importance of accurate shielding estimates.

Chenette, D. L.↗
NASA NTRS1984

The Single Event Upset (SEU) response to 590 MeV protons

The presence of high-energy protons in cosmic rays, solar flares, and trapped radiation belts around Jupiter poses a threat to the Galileo project. Results of a test of 10 device types (including 1K RAM, 4-bit microP sequencer, 4-bit slice, 9-bit data register, 4-bit shift register, octal flip-flop, and 4-bit counter) exposed to 590 MeV protons at the Swiss Institute of Nuclear Research are presented to clarify the picture of SEU response to the high-energy proton environment of Jupiter. It is concluded that the data obtained should remove the concern that nuclear reaction products generated by protons external to the device can cause significant alteration in the device SEU response. The data also show only modest increases in SEU cross section as proton energies are increased up to the upper limits of energy for both the terrestrial and Jovian trapped proton belts.

Nichols, D. K.↗
NASA NTRS1987

Experimental evidence for a new single-event upset (SEU) mode in a CMOS SRAM obtained from model verification

Modeling of SEU has been done in a CMOS static RAM containing 1-micron-channel-length transistors fabricated from a p-well epilayer process using both circuit-simulation and numerical-simulation techniques. The modeling results have been experimentally verified with the aid of heavy-ion beams obtained from a three-stage tandem van de Graaff accelerator. Experimental evidence for a novel SEU mode in an ON n-channel device is presented.

Zoutendyk, J. A.↗
NASA NTRS1987

Single-event upset (SEU) in a DRAM with on-chip error correction

Results are given of SEU measurements on 256K dynamic RAMs with on-chip error correction. They are claimed to be the first ever reported. A (12/8) Hamming error-correcting code was incorporated in the layout. Physical separation of the bits in each code word was used to guard against multiple bits being disrupted in any given word. Significant reduction in observed errors is reported.

Zoutendyk, J. A.↗
NASA NTRS1987

Single event upset (SEU) testing at JPL

It is believed that the increase in SEUs with more modern devices may have serious consequences for future space missions. The physics behind an SEU is discussed as well as SEU test philosophy and equipment, and testing results. It is concluded that the problem may be ameliorated by careful device selection and the use of redundancy or error correction.

Coss, James R.↗
NASA NTRS1988

Investigation of single-event upset (SEU) in an advanced bipolar process

An extensive analytical and experimental study SEU in an advanced silicon bipolar process was made. The modeling used process and device parameters to model the SEU charge, collection, and circuit response derived from a special version of PISCES in cylindrical coordinates and SPICE, respectively. Data are reported for test cells of various sizes.

Zoutendyk, John A.↗
NASA NTRS2006

Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

SEU from heavy-ions is measured for SOI PowerPC microprocessors. Results for 0.13 micron PowerPC with 1.1V core voltages increases over 1.3V versions. This suggests that improvement in SEU for scaled devices may be reversed. In recent years there has been interest in the possible use of unhardened commercial microprocessors in space because of their superior performance compared to hardened processors. However, unhardened devices are susceptible to upset from radiation space. More information is needed on how they respond to radiation before they can be used in space. Only a limited number of advanced microprocessors have been subjected to radiation tests, which are designed with lower clock frequencies and higher internal core voltage voltages than recent devices [1-6]. However the trend for commercial Silicon-on-insulator (SOI) microprocessors is to reduce feature size and internal core voltage and increase the clock frequency. Commercial microprocessors with the PowerPC architecture are now available that use partially depleted SOI processes with feature size of 90 nm and internal core voltage as low as 1.0 V and clock frequency in the GHz range. Previously, we reported SEU measurements for SOI commercial PowerPCs with feature size of 0.18 and 0.13 m [7, 8]. The results showed an order of magnitude reduction in saturated cross section compared to CMOS bulk counterparts. This paper examines SEUs in advanced commercial SOI microprocessors, focusing on SEU sensitivity of D-Cache and hangs with feature size and internal core voltage. Results are presented for the Motorola SOI processor with feature sizes of 0.13 microns and internal core voltages of 1.3 and 1.1 V. These results are compared with results for the Motorola SOI processors with feature size of 0.18 microns and internal core voltage of 1.6 and 1.3 V.

Irom, Farokh↗
NASA NTRS1993

Single Event Upset Behavior of CMOS Static RAM Cells

An improved state-space analysis of the CMOS static RAM cell is presented. Introducing theconcept of the dividing line, the critical charge for heavy-ion-induced upset of memory cells can becalculated considering symmetrical as well as asymmetrical capacitive loads. From the criticalcharge, the upset-rate per bit-day for static RAMs can be estimated.

Lieneweg, Udo↗
NASA NTRS2009

Radiation tolerant combinational logic cell

A system has a reduced sensitivity to Single Event Upset and/or Single Event Transient(s) compared to traditional logic devices. In a particular embodiment, the system includes an input, a logic block, a bias stage, a state machine, and an output. The logic block is coupled to the input. The logic block is for implementing a logic function, receiving a data set via the input, and generating a result f by applying the data set to the logic function. The bias stage is coupled to the logic block. The bias stage is for receiving the result from the logic block and presenting it to the state machine. The state machine is coupled to the bias stage. The state machine is for receiving, via the bias stage, the result generated by the logic block. The state machine is configured to retain a state value for the system. The state value is typically based on the result generated by the logic block. The output is coupled to the state machine. The output is for providing the value stored by the state machine. Some embodiments of the invention produce dual rail outputs Q and Q'. The logic block typically contains combinational logic and is similar, in size and transistor configuration, to a conventional CMOS combinational logic design. However, only a very small portion of the circuits of these embodiments, is sensitive to Single Event Upset and/or Single Event Transients.

Maki, Gary R.↗