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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
NASA NTRS1991

Neural Networks Of VLSI Components

Concept for design of electronic neural network calls for assembly of very-large-scale integrated (VLSI) circuits of few standard types. Each VLSI chip, which contains both analog and digital circuitry, used in modular or "building-block" fashion by interconnecting it in any of variety of ways with other chips. Feedforward neural network in typical situation operates under control of host computer and receives inputs from, and sends outputs to, other equipment.

Eberhardt, Silvio P.↗
NASA NTRS2013

Fast, High-Precision Readout Circuit for Detector Arrays

The GEO-CAPE mission described in NASA's Earth Science and Applications Decadal Survey requires high spatial, temporal, and spectral resolution measurements to monitor and characterize the rapidly changing chemistry of the troposphere over North and South Americas. High-frame-rate focal plane arrays (FPAs) with many pixels are needed to enable such measurements. A high-throughput digital detector readout integrated circuit (ROIC) that meets the GEO-CAPE FPA needs has been developed, fabricated, and tested. The ROIC is based on an innovative charge integrating, fast, high-precision analog-to-digital circuit that is built into each pixel. The 128×128-pixel ROIC digitizes all 16,384 pixels simultaneously at frame rates up to 16 kHz to provide a completely digital output on a single integrated circuit at an unprecedented rate of 262 million pixels per second. The approach eliminates the need for off focal plane electronics, greatly reducing volume, mass, and power compared to conventional FPA implementations. A focal plane based on this ROIC will require less than 2 W of power on a 1×1-cm integrated circuit. The ROIC is fabricated of silicon using CMOS technology. It is designed to be indium bump bonded to a variety of detector materials including silicon PIN diodes, indium antimonide (InSb), indium gallium arsenide (In- GaAs), and mercury cadmium telluride (HgCdTe) detector arrays to provide coverage over a broad spectral range in the infrared, visible, and ultraviolet spectral ranges.

Rider, David M.↗
DOE OSTI2026

Large-scale real-time signal processing in physics experiments: the ALICE TPC FPGA pipeline

For LHC Run 3, the ALICE Time Projection Chamber was upgraded to operate in continuous readout mode. Interaction rates of up to 50 kHz in Pb-Pb collisions require real-time processing of more than 3 TB s -1 of raw detector data. This requirement is met by a custom FPGA-based processing pipeline that performs the complete front-end data treatment fully in-stream, including common-mode correction, pedestal subtraction, ion-tail filtering, zero suppression, and dense data packing. A central element of the design is a highly parallel common-mode correction algorithm operating directly on the streaming data. It robustly identifies signal-free readout channels on a time-bin basis and applies pad-dependent scaling to compensate for local variations in capacitive coupling in the GEM readout. In combination with pedestal subtraction and ion-tail filtering, this enables accurate baseline restoration under extreme high-occupancy conditions, preventing signal loss while efficiently suppressing noise prior to zero suppression. The pipeline operates continuously at the full detector bandwidth and reduces the raw input rate of approximately 3 TB s -1 to about 900 GBps for Pb-Pb collisions at the target interaction rate. Overall, it represents a large-scale FPGA-based real-time signal-processing implementation for high-energy physics detector readout.

Digital signal processing (DSP)↗
NASA NTRS1979

An introduction to the BANNING design automation system for shuttle microelectronic hardware development

The BANNING MOS design system is presented. It complements rather than supplant the normal design activities associated with the design and fabrication of low-power digital electronic equipment. BANNING is user-oriented and requires no programming experience to use effectively. It provides the user a simulation capability to aid in his circuit design and it eliminates most of the manual operations involved in the layout and artwork generation of integrated circuits. An example of its operation is given and some additional background reading is provided.

Mcgrady, W. J.↗
NASA NTRS1980

Space applications of superconductivity - Digital electronics

Superconducting electronics offers a variety of remarkable properties including high speed and low dissipation. The paper discusses fundamental considerations which appear to suggest that superconducting (cryogenic) technology will offer significant advantages for future digital devices. It shows how the active element in superconducting electronics, the Josephson junction, works and discusses the technology for fabricating the devices. The characteristics of published circuits are briefly reviewed, and the capabilities of future superconducting computers and instruments are projected.

Harris, R. E.↗
NASA NTRS2010

Electrical Capacitance Volume Tomography with High-Contrast Dielectrics

The Electrical Capacitance Volume Tomography (ECVT) system has been designed to complement the tools created to sense the presence of water in nonconductive spacecraft materials, by helping to not only find the approximate location of moisture but also its quantity and depth. The ECVT system has been created for use with a new image reconstruction algorithm capable of imaging high-contrast dielectric distributions. Rather than relying solely on mutual capacitance readings as is done in traditional electrical capacitance tomography applications, this method reconstructs high-resolution images using only the self-capacitance measurements. The image reconstruction method assumes that the material under inspection consists of a binary dielectric distribution, with either a high relative dielectric value representing the water or a low dielectric value for the background material. By constraining the unknown dielectric material to one of two values, the inverse math problem that must be solved to generate the image is no longer ill-determined. The image resolution becomes limited only by the accuracy and resolution of the measurement circuitry. Images were reconstructed using this method with both synthetic and real data acquired using an aluminum structure inserted at different positions within the sensing region. The cuboid geometry of the system has two parallel planes of 16 conductors arranged in a 4 4 pattern. The electrode geometry consists of parallel planes of copper conductors, connected through custom-built switch electronics, to a commercially available capacitance to digital converter. The figure shows two 4 4 arrays of electrodes milled from square sections of copper-clad circuit-board material and mounted on two pieces of glass-filled plastic backing, which were cut to approximately square shapes, 10 cm on a side. Each electrode is placed on 2.0-cm centers. The parallel arrays were mounted with the electrode arrays approximately 3 cm apart. The open ends were surrounded by a metal guard to reduce the sensitivity of the electrodes to outside interference and to help maintain the spacing between the arrays. Other uses for this innovation potentially include quantifying the amount of commodity remaining in the fuel and oxidizer tanks while on-orbit without having to fire spacecraft engines. Another orbit application is moisture sensing in plant-growth experiments because microgravity causes moisture in soil to distribute itself in unusual ways. At the moment, the hardware and image reconstruction technique may only be of interest to people involved in nondestructive evaluation. The reconstructed image takes almost a full week to reproduce with existing computer power. However, because computer power and speeds follows Moore s Law, execution times are likely to become acceptable within the next five to eight years. The code was written in Mathematica for dedicated use with the ECVT system. In its present form, it is not suitable to be used directly as a consumer product. However, the code could be likely improved by rewriting it in a compiled language such as C or Fortran.

Nurge, Mark↗
NASA NTRS1993

Optoelectronic Control Of Phased-Array Antenna

Radiation patterns switched within microseconds. According to concept, digital beam-steering information destined for number of phased antenna elements transmitted in serial multiplex along optical fiber to optoelectronic integrated circuit (OEIC), demultiplexing information into parallel electronic channels to phase shifters associated with various elements. Because of small distances between elements of such arrays, compactness of optical fibers makes them attractive for distribution of beam-steering (phase-shifting) control signals. Also offers advantages of light weight, low attenuation, mechanical flexibility, large bandwidth, and immunity to both crosstalk and electromagnetic interference.

Bhasin, K. B.↗
NASA NTRS1982

Electron lithography STAR design guidelines. Part 2: The design of a STAR for space applications

The STAR design system developed by NASA enables any user with a logic diagram to design a semicustom digital MOS integrated circuit. The system is comprised of a library of standard logic cells and computr programs to place, route, and display designs implemented with cells from the library. Also described is the development of a radiation-hard array designed for the STAR system. The design is based on the CMOS silicon gate technology developed by SANDIA National Laboratories. The design rules used are given as well as the model parameters developed for the basic array element. Library cells of the CMOS metal gate and CMOS silicon gate technologies were simulated using SPICE, and the results are shown and compared.

Trotter, J. D.↗
NASA NTRS2003

SpaceWire Driver Software for Special DSPs

A computer program provides a high-level C-language interface to electronics circuitry that controls a SpaceWire interface in a system based on a space qualified version of the ADSP-21020 digital signal processor (DSP). SpaceWire is a spacecraft-oriented standard for packet-switching data-communication networks that comprise nodes connected through bidirectional digital serial links that utilize low-voltage differential signaling (LVDS). The software is tailored to the SMCS-332 application-specific integrated circuit (ASIC) (also available as the TSS901E), which provides three highspeed (150 Mbps) serial point-to-point links compliant with the proposed Institute of Electrical and Electronics Engineers (IEEE) Standard 1355.2 and equivalent European Space Agency (ESA) Standard ECSS-E-50-12. In the specific application of this software, the SpaceWire ASIC was combined with the DSP processor, memory, and control logic in a Multi-Chip Module DSP (MCM-DSP). The software is a collection of low-level driver routines that provide a simple message-passing application programming interface (API) for software running on the DSP. Routines are provided for interrupt-driven access to the two styles of interface provided by the SMCS: (1) the "word at a time" conventional host interface (HOCI); and (2) a higher performance "dual port memory" style interface (COMI).

Clark, Douglas↗
NASA NTRS1991

Compensated digital readout family

ISC has completed test on an IC which has 32 channels of amplifiers, low pass anti-aliasing filters, 13-bit analog-to-digital (A/D) converters with non-uniformity correction per channel and a digital multiplexer. The single slope class of A/D conversion is described, as are the unique variations required for incorporation of this technique for use with on-focal plane detector readout electronics. This paper describes the architecture used to implement the digital on-focal plane signal processing functions. Results from measured data on a test IC are presented for a circuit containing these functions operating at a sensor frame rate of 1000 hertz.

Ludwig, David E.↗
NASA NTRS1975

Microelectronic fabrication of superconducting devices and circuits

It is expected that thin-film superconductors can be used as detectors or sources of infrared and microwave radiation, as magnetometers, as voltage standards, and for voltage and current measurements, for electronic signal processing, and in digital circuitry.

Kirschman, R. K.↗
NASA NTRS1996

Compiled Data On Single-Event Effects Caused By Heavy Ions

Report presents test data on susceptibility of new set of digital integrated circuits and other semiconductor products to single-event effects (soft errors and latchups) caused by heavy ions incident at high energies. Data used to develop generalizations for protecting electronic equipment from single-event effects. In some cases, tested parts selected as candidates for use in specific applications.

Nichols, Donald K.↗
NASA NTRS2017

Single-Event Latchup Measurements on COTS Electronic Devices for Use in ISS Payloads

This paper reports recent single-event latchup results for a variety of microelectronic devices that include an ADC, OpAmp, EEPROM, CPLD, PWM, transceiver, voltage regulator, digital signal processor, step-down converter, buck controller and supervisory circuits. The data were collected to evaluate these devices for possible use in NASA ISS payloads.

Irom, Farokh↗
NASA NTRS1993

Design methods for fault-tolerant finite state machines

VLSI electronic circuits are increasingly being used in space-borne applications where high levels of radiation may induce faults, known as single event upsets. In this paper we review the classical methods of designing fault tolerant digital systems, with an emphasis on those methods which are particularly suitable for VLSI-implementation of finite state machines. Four methods are presented and will be compared in terms of design complexity, circuit size, and estimated circuit delay.

Niranjan, Shailesh↗
NASA NTRS2004

Stroboscope Controller for Imaging Helicopter Rotors

A versatile electronic timing-and-control unit, denoted a rotorcraft strobe controller, has been developed for use in controlling stroboscopes, lasers, video cameras, and other instruments for capturing still images of rotating machine parts especially helicopter rotors. This unit is designed to be compatible with a variety of sources of input shaftangle or timing signals and to be capable of generating a variety of output signals suitable for triggering instruments characterized by different input-signal specifications. It is also designed to be flexible and reconfigurable in that it can be modified and updated through changes in its control software, without need to change its hardware. Figure 1 is a block diagram of the rotorcraft strobe controller. The control processor is a high-density complementary metal oxide semiconductor, singlechip 8-bit microcontroller. It is connected to a 32K x 8 nonvolatile static random-access memory (RAM) module. Also connected to the control processor is a 32K 8 electrically programmable read-only-memory (EPROM) module, which is used to store the control software. Digital logic support circuitry is implemented in a field-programmable gate array (FPGA). A 240 x 128-dot, 40- character 16-line liquid-crystal display (LCD) module serves as a graphical user interface; the user provides input through a 16-key keypad mounted next to the LCD. A 12-bit digital-to-analog converter (DAC) generates a 0-to-10-V ramp output signal used as part of a rotor-blade monitoring system, while the control processor generates all the appropriate strobing signals. Optocouplers are used to isolate all input and output digital signals, and optoisolators are used to isolate all analog signals. The unit is designed to fit inside a 19-in. (.48-cm) rack-mount enclosure. Electronic components are mounted on a custom printed-circuit board (see Figure 2). Two power-conversion modules on the printedcircuit board convert AC power to +5 VDC and 15 VDC, respectively.

Jensen, Scott↗
DOE OSTI2025

Unconventional compute methods and future challenges for superconducting digital computing

Superconducting digital computing (SDC) based on Josephson junctions (JJs) offers significant potential for enhancing compute throughput and reducing energy consumption compared to conventional room-temperature CMOS-based approaches. Current superconducting logic families exhibit diverse characteristics in clocking strategies, power management, and information encoding techniques. This paper reviews recent advancements in unconventional computing methods specifically designed for superconducting digital circuits, emphasizing temporal computing and pulse-train representations. Notable techniques include race logic (RL), temporal pulse train computing (U-SFQ), and temporal multipliers, each offering unique performance and area advantages suited to superconducting implementations. Additionally, this paper reviews innovations in superconducting coarse-grain reconfigurable architectures (CGRA), superconducting-specific on-chip communication architectures, cryogenic sensor interfaces, and quantum computing control electronics. Finally, we highlight research challenges that should be addressed to facilitate the widespread adoption of superconducting digital computing.

EDA tools↗
NASA NTRS1976

Electronic system for optical shutter control

The paper describes a precise and versatile electronic system for shutter control in light beam experiments. Digital and analog circuitry is used to provide automatic timing, exposure control, manual operation, and remote programmability. A block diagram of the system is presented and the individual circuits - the timer control circuit, the clock control circuit, the comparator circuit, the exposure (integrator) circuit, and the shutter drive circuit are discussed in detail and diagrams are provided.

Viljoen, H. C.↗