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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
NASA NTRS1986

Flat-plate solar array project process development area: Process research of non-CZ silicon material

Several different techniques to simultaneously diffuse the front and back junctions in dendritic web silicon were investigated. A successful simultaneous diffusion reduces the cost of the solar cell by reducing the number of processing steps, the amount of capital equipment, and the labor cost. The three techniques studied were: (1) simultaneous diffusion at standard temperatures and times using a tube type diffusion furnace or a belt furnace; (2) diffusion using excimer laser drive-in; and (3) simultaneous diffusion at high temperature and short times using a pulse of high intensity light as the heat source. The use of an excimer laser and high temperature short time diffusion experiment were both more successful than the diffusion at standard temperature and times. The three techniques are described in detail and a cost analysis of the more successful techniques is provided.

Campbell, R. B.↗
NASA NTRS2008

SiC JFET Transistor Circuit Model for Extreme Temperature Range

A technique for simulating extreme-temperature operation of integrated circuits that incorporate silicon carbide (SiC) junction field-effect transistors (JFETs) has been developed. The technique involves modification of NGSPICE, which is an open-source version of the popular Simulation Program with Integrated Circuit Emphasis (SPICE) general-purpose analog-integrated-circuit-simulating software. NGSPICE in its unmodified form is used for simulating and designing circuits made from silicon-based transistors that operate at or near room temperature. Two rapid modifications of NGSPICE source code enable SiC JFETs to be simulated to 500 C using the well-known Level 1 model for silicon metal oxide semiconductor field-effect transistors (MOSFETs). First, the default value of the MOSFET surface potential must be changed. In the unmodified source code, this parameter has a value of 0.6, which corresponds to slightly more than half the bandgap of silicon. In NGSPICE modified to simulate SiC JFETs, this parameter is changed to a value of 1.6, corresponding to slightly more than half the bandgap of SiC. The second modification consists of changing the temperature dependence of MOSFET transconductance and saturation parameters. The unmodified NGSPICE source code implements a T(sup -1.5) temperature dependence for these parameters. In order to mimic the temperature behavior of experimental SiC JFETs, a T(sup -1.3) temperature dependence must be implemented in the NGSPICE source code. Following these two simple modifications, the Level 1 MOSFET model of the NGSPICE circuit simulation program reasonably approximates the measured high-temperature behavior of experimental SiC JFETs properly operated with zero or reverse bias applied to the gate terminal. Modification of additional silicon parameters in the NGSPICE source code was not necessary to model experimental SiC JFET current-voltage performance across the entire temperature range from 25 to 500 C.

Neudeck, Philip G.↗
NASA NTRS1977

Application of the SEM to the measurement of solar cell parameters

Techniques are described which make use of the SEM to measure the minority carrier diffusion length and the metallurgical junction depth in silicon solar cells. The former technique permits the measurement of the true bulk diffusion length through the application of highly doped field layers to the back surfaces of the cells being investigated. It is shown that the secondary emission contrast observed in the SEM on a reverse-biased diode can depict the location of the metallurgical junction if the diode has been prepared with the proper beveled geometry. The SEM provides the required contrast and the option of high magnification, permitting the measurement of extremely shallow junction depths.

Weizer, V. G.↗
NASA NTRS1961

A Technique for Increasing the Sensitivity of a Solid-State Fission Probe

A small silicon p-n junction wafer, when coated with uranium 235, can be used as a compact fission probe for low power flux and power mapping. Because of the inverse relation between the magnitude of a neutron-induced fission pulse and the inherent capacitance of the detecting element (capacitance is proportional to area), the size, and hence the sensitivity, of the semiconductor detector has been limited. New developments in the field of semiconductor detectors have made it possible to fabricate large area detectors which are essentially free from the capacitance effect. However, preliminary results indicate that they are much more susceptible to radiation damage than the detectors described in this report and as such may not be suitable for flux mapping. increasing the sensitivity cannot be accomplished by simply fabricating a larger detector. It has been observed that by combining the silicon p-n junction wafers in a series configuration the capacitance effect can be bypassed, and a fission probe can be made with a resultant increase in sensitivity by a factor of ten while sustaining only a minor decrease in pulse height. Analysis further indicates that for n silicon wafers in series, if n(C(sub i)) + C(sub c)/C(sub b) less than 0.1 where C(sub i) and C(sub c) are the preamplifier input and cable capacitances, respectively, and C(sub b) is the junction capacitance of a single silicon wafer, there should be no substantial reduction in pulse height due to series circuitry.

Steinberg, Robert↗
NASA NTRS1977

Application of the SEM to the measurement of solar cell parameters

A pair of techniques are described which make use of the SEM to measure, respectively, the minority carrier diffusion length and the metallurgical junction depth in silicon solar cells. The former technique permits the measurement of the true bulk diffusion length through the application of highly doped field layers to the back surfaces of the cells being investigated. The technique yields an absolute value of the diffusion length from a knowledge of the collected fraction of the injected carriers and the cell thickness. It is shown that the secondary emission contrast observed in the SEM on a reverse-biased diode can depict the location of the metallurgical junction if the diode has been prepared with the proper beveled geometry. The SEM provides the required contrast and the option of high magnification, permitting the measurement of extremely shallow junction depths.

Weizer, V. G.↗
NASA NTRSDate not supplied

Progress Towards SiC ASICs for Extreme Temperature and Radiation Environments

This presentation describes development and demonstrations of semiconductor integrated circuits (ICs) and ceramic packaging that are arguably the most environmentally durable transistor electronics ever demonstrated. Silicon carbide (SiC) junction field effect transistor-resistor (JFET-R) ICs fabricated by NASA Glenn Research Center with two-level interconnect have successfully operated for over 1 year in 500 °C air-ambient, 60 days in 460 °C and 9.3 MPa pressure caustic Venus surface environment test chamber, and radiation exposure through 7 Mrad(Si) total ionizing dose (TID) and 86 MeV-cm2/mg heavy ion strikes. Furthermore, these ICs have also demonstrated operation from -190 °C to +812 °C (over 1000 °C temperature span) without significant change in signal (input /output) or power supply voltages. While the operating frequency and functional complexity is far below silicon-based ICs, these SiC application specific ICs (ASICs) are nevertheless becoming capable of providing unique and advantageous harsh-environment circuit functionality without cooling/sheltering overhead. With modest adjustments, the SiC JFET-R fabrication process is compatible with semiconductor mass-production tools and materials. As an initial step towards manufacture, a majority of processing steps to realize the next SiC JFET-R IC prototype wafer run have been outsourced to commercial foundry. It is expected that further upscaling combined with technology transfer to commercial production will lower investment and risk barriers to useful application deployment.

high temperature↗
NASA NTRS2015

4H-SiC JFET Multilayer Integrated Circuit Technologies Tested Up to 1000 K

Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 C) and 1150K (877 C) with successful electrical operation of all devices observed up to 1000K (727 C).

JFET↗
DOE OSTI2024

Resolving the Electron Plume within a Scanning Electron Microscope

Scanning electron microscopy (SEM), a century-old technique, is today a ubiquitous method of imaging the surface of nanostructures. However, most SEM detectors simply count the number of secondary electrons from a material of interest, and thereby overlook the rich material information contained within them. Here, by simple modifications to a standard SEM tool, we resolve the momentum and energy information on secondary electrons by directly imaging the electron plume generated by the electron beam of the SEM. Leveraging these spectroscopic imaging capabilities, our technique is able to image lateral electric fields across a prototypical silicon p–n junctions and to distinguish differently doped regions, even when buried beyond depths typically accessible by SEM. Intriguingly, the subsurface sensitivity of this technique reveals unexpectedly strong surface band bending within nominally passivated semiconductor structures, providing useful insights for complex layered component designs, in which interfacial dynamics dictate device operation. Further, these capabilities for noninvasive, multimodal probing of complicated electronic components are crucial in today’s electronic manufacturing but is largely inaccessible even with sophisticated techniques. These results show that seemingly simple SEM can be extended to probe complex and useful material properties.

36 MATERIALS SCIENCE↗
NASA NTRS1982

Computer-aided prediction of high-frequency performance limits in silicon bipolar integrated circuits

A circuit model for an existing silicon integrated bipolar junction transistor (IBJT) is used to evaluate presently achievable high frequency circuit performance. The relationship between circuit model and processing parameters are semi-quantitatively explored to make predictions on the frequency response, which can be achieved through realistic device fabrication modifications. A new figure of merit is introduced, which is defined as the signal frequency at which an integrated bipolar junction transistor can deliver a power gain of G. The most sensitive parameter influencing attainable high frequency IBJT performance is base resistance.

Burns, J. L.↗
NASA NTRS1982

Non-mass-analyzed ion implantation equipment for high volume solar cell production

Equipment designed for junction formation in silicon solar cells is described. The equipment, designed for a production level of approximately one megawatt per year, consists of an ion implanter and annealer. Low cost is achieved by foregoing the use of mass analysis during the implantation, and by the use of a belt furnace for annealing. Results of process development, machine design and cost analysis are presented.

Armini, A. J.↗
NASA NTRS1988

The effect of different module configurations on the radiation tolerance of multijunction solar cells

The effect of different module configurations on the performance of multijunction (MJ) solar cells in a radiation environment was investigated. Module configuration refers to the electrical circuit in which the subcells of the multijunction cell are wired. Experimental data for AlCaAs, GaAs, InGaAs, and silicon single-junction concentrator cells subjected to 1 MeV electron irradiation was used to calculate the expected performance of AlGaAs/InGaAs, AlGa/silicon, GaAs/InGaAs, and GaAs/silicon Mj concentrator cells. These calculations included independent, series, and voltage-matched configurations. The module configuration was found to have a significant impact on the radiation tolerance characteristic of the MJ cells.

Gee, James M.↗
NASA NTRS2021

Practical SiC JFET-R Analog Integrated Circuit Design for Extreme Environment Applications

Silicon carbide (SiC) junction field effect transistor and SiC resistor (SiC JFET-R) integrated circuits(ICs) have uniquely demonstrated prolonged operation above 450 °C that promises significant operational improvements to a variety of NASA missions. However, the SiC epiwafers used to fabricate these ICs suffer from epi-growth process immaturity that imparts large and systematic spreads in JFET threshold voltages as a function of the device distance from the center on the wafer. Furthermore, the unprecedently wide range of intended application operating temperatures (in many cases over 600 °C wide) imparts as much as 5-fold change in JFET bias currents. This Technical Memorandum documents methods by which both temperature and radius associated JFET electrical parameter variances can be adequately eliminated, or even exploited in JFET-R circuit designs. Full analog circuit examples, including operational amplifiers, and SPICE simulations across experimentally documented SiC JFET parameter extremes are given to illustrate the efficacy of these methods. The reader may use the examples in this memorandum as either an end point, to get a desired analog signal conditioning design into hardware implemented in SiC JFET-R ICs, or as a basis point from which to derive further improvement.

Michael J Krasowski↗