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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
NASA NTRS1980

Flat-plate photovoltaic array design optimization

An analysis is presented which integrates the results of specific studies in the areas of photovoltaic structural design optimization, optimization of array series/parallel circuit design, thermal design optimization, and optimization of environmental protection features. The analysis is based on minimizing the total photovoltaic system life-cycle energy cost including repair and replacement of failed cells and modules. This approach is shown to be a useful technique for array optimization, particularly when time-dependent parameters such as array degradation and maintenance are involved.

Ross, R. G., Jr.↗
NASA NTRS1991

An improved offset generator developed for Allan deviation measurement of ultra stable frequency standards

Measuring the performance of ultra stable frequency standards such as the Superconducting Cavity Maser Oscillator (SCMO) necessitates improvement of some test instrumentation. The frequency stability test equipment used at JPL includes a 1 Hz Offset Generator to generate a beat frequency between a pair of 100 MHz signals that are being compared. The noise floor of the measurement system using the current Offset Generator is adequate to characterize stability of hydrogen masers, but it is not adequate for the SCMO. A new Offset Generator with improved stability was designed and tested at JPL. With this Offset Generator and a new Zero Crossing Detector, recently developed at JPL, the measurement flow was reduced by a factor of 5.5 at 1 second tau, 3.0 at 1000 seconds, and 9.4 at 10,000 seconds, compared against the previous design. In addition to the new circuit designs of the Offset Generator and Zero Crossing Detector, tighter control of the measurement equipment environment was required to achieve this improvement. The design of this new Offset Generator are described, along with details of the environment control methods used.

R. L. Hamell↗
NASA NTRS1988

Designing A Microwave Band-Stop Filter

Lumped-circuit design techniques applied to iris-coupled cavities. Waveguide/cavity filter imitates lumped series and parallel combinations of inductance and capacitance over narrow stopband centered at 7.190 GHz. Filter made of standard WR125 waveguide stock.

Manshadi, F.↗
NASA NTRS2006

Testing and Qualifying Linear Integrated Circuits for Radiation Degradation in Space

This paper discusses mechanisms and circuit-related factors that affect the degradation of linear integrated circuits from radiation in space. For some circuits there is sufficient degradation to affect performance at total dose levels below 4 krad(Si) because the circuit design techniques require higher gain for the pnp transistors that are the most sensitive to radiation. Qualification methods are recommended that include displacement damage as well as ionization damage.

integrated circuit testing↗
NASA NTRS1986

GaAs Semi-Insulating Layer for a GaAs Device

Improved design for GaAs electronic device or integrated circuit designed to operate at cryogenic temperatures, customary SiO2 insulating layer replaced by semi-insulating layer of GaAs. Thermal expansions of device and covering layer therefore match closely, and thermal stresses caused by immersion in cryogenic chamber nearly eliminated.

Sherrill, G.↗
NASA NTRS1985

Advanced on-site power plant development technology program

A 30-cell stack was tested for 7200 hours. At 6000 hours the stack was successfully refilled with acid with no loss of performance. A second stack containing the advanced Configuration B cell package was fabricated and assembled for testing in 1985. A 200-kW brassboard inverter was successfully evaluated, verifying the design of the two-bridge ASCR circuit design. A fuel processing catalyst train was tested for 2000 hours verifying the catalyst for use in a 200-kW development reformer. The development reformer was fabricated for evaluation in 1985. The initial test plan was prepared for a 200-kW verification test article.

Kemp, F. S.↗
NASA NTRS1995

Millimeter And Submillimeter-Wave Integrated Circuits On Quartz

Proposed Quartz substrate Upside-down Integrated Device (QUID) relies on UV-curable adhesive to bond semiconductor with quartz. Integrated circuits including planar GaAs Schottky diodes and passive circuit elements (such as bandpass filters) fabricated on quartz substrates. Circuits designed to operate as mixers in waveguide circuit at millimeter and submillimeter wavelengths. Integrated circuits mechanically more robust, larger, and easier to handle than planar Schottky diode chips. Quartz substrate more suitable for waveguide circuits than GaAs substrate.

Mehdi, Imran↗
NASA NTRS2012

Verilog-A Device Models for Cryogenic Temperature Operation of Bulk Silicon CMOS Devices

Verilog-A based cryogenic bulk CMOS (complementary metal oxide semiconductor) compact models are built for state-of-the-art silicon CMOS processes. These models accurately predict device operation at cryogenic temperatures down to 4 K. The models are compatible with commercial circuit simulators. The models extend the standard BSIM4 [Berkeley Short-channel IGFET (insulated-gate field-effect transistor ) Model] type compact models by re-parameterizing existing equations, as well as adding new equations that capture the physics of device operation at cryogenic temperatures. These models will allow circuit designers to create optimized, reliable, and robust circuits operating at cryogenic temperatures.

Akturk, Akin↗
NASA NTRS2014

SpaceCube v2.0 Space Flight Hybrid Reconfigurable Data Processing System

This paper details the design architecture, design methodology, and the advantages of the SpaceCube v2.0 high performance data processing system for space applications. The purpose in building the SpaceCube v2.0 system is to create a superior high performance, reconfigurable, hybrid data processing system that can be used in a multitude of applications including those that require a radiation hardened and reliable solution. The SpaceCube v2.0 system leverages seven years of board design, avionics systems design, and space flight application experiences. This paper shows how SpaceCube v2.0 solves the increasing computing demands of space data processing applications that cannot be attained with a standalone processor approach.The main objective during the design stage is to find a good system balance between power, size, reliability, cost, and data processing capability. These design variables directly impact each other, and it is important to understand how to achieve a suitable balance. This paper will detail how these critical design factors were managed including the construction of an Engineering Model for an experiment on the International Space Station to test out design concepts. We will describe the designs for the processor card, power card, backplane, and a mission unique interface card. The mechanical design for the box will also be detailed since it is critical in meeting the stringent thermal and structural requirements imposed by the processing system. In addition, the mechanical design uses advanced thermal conduction techniques to solve the internal thermal challenges.The SpaceCube v2.0 processing system is based on an extended version of the 3U cPCI standard form factor where each card is 190mm x 100mm in size The typical power draw of the processor card is 8 to 10W and scales with application complexity. The SpaceCube v2.0 data processing card features two Xilinx Virtex-5 QV Field Programmable Gate Arrays (FPGA), eight memory modules, a monitor FPGA with analog monitoring, Ethernet, configurable interconnect to the Xilinx FPGAs including gigabit transceivers, and the necessary voltage regulation. The processor board uses a back-to-back design methodology for common parts that maximizes the board real estate available. This paper will show how to meet the IPC 6012B Class 3A standard with a 22-layer board that has two column grid array devices with 1.0mm pitch. All layout trades such as stack-up options, via selection, and FPGA signal breakout will be discussed with feature size results. The overall board design process will be discussed including parts selection, circuit design, proper signal termination, layout placement and route planning, signal integrity design and verification, and power integrity results. The radiation mitigation techniques will also be detailed including configuration scrubbing options, Xilinx circuit mitigation and FPGA functional monitoring, and memory protection.Finally, this paper will describe how this system is being used to solve the extreme challenges of a robotic satellite servicing mission where typical space-rated processors are not sufficient enough to meet the intensive data processing requirements. The SpaceCube v2.0 is the main payload control computer and is required to control critical subsystems such as autonomous rendezvous and docking using a suite of vision sensors and object avoidance when controlling two robotic arms.

Xilinx FPGA↗
NASA NTRS2001

Micromachined TWTs for THz Radiation Sources

The Terahertz (THz) region of the electromagnetic spectrum (about 300 - 3000 GHz in frequency or about 0.1 - 1 mm free space wavelength) has enormous potential for high-data-rate communications, spectroscopy, astronomy, space research, medicine, biology, surveillance, remote sensing, industrial process control, etc. It has been characterized as the most scientifically rich, yet under-utilized, region of the electromagnetic spectrum. The most critical roadblock to full exploitation of the THz band is lack of coherent radiation sources that are powerful (0.001 - 1.0 W continuous wave), efficient (> 1%), frequency agile (instantaneously tunable over 1% bandwidths or more), reliable, and comparatively inexpensive. To develop vacuum electron device (VED) radiation sources satisfying these requirements, fabrication and packaging approaches must be heavily considered to minimize costs, in addition to the basic interaction physics and circuit design. To minimize size of the prime power supply, beam voltage must be minimized, preferably 10 kV. Solid state sources satisfy the low voltage requirement, but are many orders of magnitude below power, efficiency, and bandwidth requirements. On the other hand, typical fast-wave VED sources in this regime (e.g., gyrotrons, FELs) tend to be large, expensive, high voltage and very high power devices unsuitable for most of the applications cited above. VEDs based on grating or inter-digital (ID) circuits have been researched and developed. However, achieving forward-wave amplifier operation with instantaneous fractional bandwidths > 1% is problematic for these devices with low-energy (< 15 kV) electron beams. Moreover, the interaction impedance is quite low unless the beam-circuit spacing is kept particularly narrow, often leading to significant beam interception. One solution to satisfy the THz source requirements mentioned above is to develop micromachined VEDs, or "micro-VEDs". Among other benefits, micro-machining technologies provide superior high frequency wall conductivity as a result of superior surface smoothness compared with conventional mechanical or electric discharge machining approaches. Micro-VED technologies are already being applied to the development of millimeter-wave klystrons at Stanford Linear Accelerator Center and submillimeter-wave klystrons at the University of Leeds. We are investigating the use of micro-machining technologies to develop THz regime TWTs, with emphasis on folded-waveguide TWTs. The folded-waveguide TWT (FW-TWT) has several features that make it attractive for THz-regime micro-VED applications. It is a relatively simple circuit to design and fabricate, it is amenable to precision pattern replication by micro-machining, and it is has been demonstrated capable of forward-wave amplification with appreciable bandwidth. We are conducting experimental and computational studies of micro-VED FW-TWTs to examine their feasibility for applications at frequencies from 200 - 1000 GHz.

Booske, John H.↗
NASA NTRS2002

Simulation Model of A Ferroelectric Field Effect Transistor

An electronic simulation model has been developed of a ferroelectric field effect transistor (FFET). This model can be used in standard electrical circuit simulation programs to simulate the main characteristics of the FFET. The model uses a previously developed algorithm that incorporates partial polarization as a basis for the design. The model has the main characteristics of the FFET, which are the current hysterisis with different gate voltages and decay of the drain current when the gate voltage is off. The drain current has values matching actual FFET's, which were measured experimentally. The input and output resistance in the model is similar to that of the FFET. The model is valid for all frequencies below RF levels. A variety of different ferroelectric material characteristics can be modeled. The model can be used to design circuits using FFET'S with standard electrical simulation packages. The circuit can be used in designing non-volatile memory circuits and logic circuits and is compatible with all SPICE based circuit analysis programs. The model is a drop in library that integrates seamlessly into a SPICE simulation. A comparison is made between the model and experimental data measured from an actual FFET.

MacLeod, Todd C.↗
NASA NTRS1980

Design rules for CMOS/SOS circuits

Report presents design rules for advanced-technology integrated circuits made by self-aligned silicongate complementary - metal - oxide - semiconductor/silicon-on-sapphir (CMOS/SOS) process.

Source record↗
NASA NTRS1976

Artwork Interactive Design System (AIDS) program description

An artwork interactive design system is described which provides the microelectronic circuit designer/engineer a tool to perform circuit design, automatic layout modification, standard cell design, and artwork verification at a graphics computer terminal using a graphics tablet at the designer/computer interface.

Johnson, B. T.↗
NASA NTRS1974

The design and development of a high voltage power supply

A high voltage circuit system was redesigned, breadboarded, and tested to meet revised specification requirements. Circuit component subassemblies are described and include the firing unit, regulator, dc to dc converter, and output and trigger circuits. Design changes, tests, and equipment fabrication are outlined chronologically by month. A list of design specifications is included.

Ting, R.↗
NASA NTRS1990

Path programmable logic: A structured design method for digital and/or mixed analog integrated circuits

The design of Integrated Circuits has evolved past the black art practiced by a few semiconductor companies to a world wide community of users. This was basically accomplished by the development of computer aided design tools which were made available to this community. As the tools matured into different components of the design task they were accepted into the community at large. However, the next step in this evolution is being ignored by the large tool vendors hindering the continuation of this process. With system level definition and simulation through the logic specification well understood, why is the physical generation so blatantly ignored. This portion of the development is still treated as an isolated task with information being passed from the designer to the layout function. Some form of result given back but it severely lacks full definition of what has transpired. The level of integration in I.C.'s for tomorrow, whether through new processes or applications will require higher speeds, increased transistor density, and non-digital performance which can only be achieved through attention to the physical implementation.

Taylor, B.↗