Recent developments in thin-film capacitors
Thin film capacitor research and development - deposition of materials for capacitor dielectrics, and materials compatibility with integrated circuits
CAPACITOR↗
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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Low-temperature thermionic emitter Final report, 9 Feb. 1969 - 9 Apr. 1970
Fabrication processes for integrated vacuum circuits and life tests of dual triodes for low temperature thermionic emitters
Nitzan, D.↗
Banning design automation software implementation
The research is reported for developing a system of computer programs to aid engineering in the design, fabrication, and testing of large scale integrated circuits, hybrid circuits, and printed circuit boards. The automatic layout programs, analysis programs, and interface programs are discussed.
Kuehlthau, R. L.↗
SEM probe of IC radiation sensitivity
Scanning Electron Microscope (SEM) used to irradiate single integrated circuit (IC) subcomponent to test for radiation sensitivity can localize area of IC less than .03 by .03 mm for determination of exact location of radiation sensitive section.
Gauthier, M. K.↗
On-Orbit Measurement of the Superconductive Transition Temperatures of YBa2Cu3O(7-x) Thick Films
Thick film superconductors were integrated into hybrid circuits and tested in the Materials In Devices As Superconductors (MIDAS) spaceflight experiment which operated autonomously aboard the MIR space station for 90 days. MIDAS was designed to cool the circuits from 300 to 75K, maintain the temperature at 75K for 28 days, and warm the circuits back to 300K. This cycle was performed a total of three times, during which the superconductive transition temperature was measured during each cool-down and warm-up portion of the experiment. All of the thick films used in this experiment exhibited superconductive transition temperatures of approximately 87K, and no significant differences in the resistance versus temperature properties of the materials were observed among the data collected during pre-flight, flight, and post-flight operations.
Hooker, Matthew W.↗
Challenges in Interconnection and Packaging of Microelectromechanical Systems (MEMS)
Integrated circuit packaging and their testing is well advanced because of the maturity of the IC industry, their wide applications, and availability of industrial infrastructure.
COTS MEMS packaging interconnections reliability↗
Packaging Technology for SiC High Temperature Electronics
High-temperature environment operable sensors and electronics are required for long-term exploration of Venus and distributed control of next generation aeronautical engines. Various silicon carbide (SiC) high temperature sensors, actuators, and electronics have been demonstrated at and above 500 C. A compatible packaging system is essential for long-term testing and application of high temperature electronics and sensors in relevant environments. This talk will discuss a ceramic packaging system developed for high temperature electronics, and related testing results of SiC integrated circuits at 500 C facilitated by this high temperature packaging system, including the most recent progress.
Chen, Liang-Yu↗
Design, processing, and testing of LSI arrays for space station
The Si-gate CMOS/SOS process used to manufacture integrated circuits is examined. A process analysis test structure is developed to determine the defect mechanisms most detrimental to yield, control, and reliability.
Ipri, A. C.↗
Design, Fabrication and Integration of a NaK-Cooled Circuit
The Early Flight Fission Test Facilities (EFF-TF) team has been tasked by the NASA Marshall Space Flight Center Nuclear Systems Office to design, fabricate, and test an actively pumped alkali metal flow circuit. The system, which was originally designed for use with a eutectic mixture of sodium potassium (NaK), was redesigned to for use with lithium. Due to a shi$ in focus, it is once again being prepared for use with NaK. Changes made to the actively pumped, high temperature circuit include the replacement of the expansion reservoir, addition of remotely operated valves, and modification of the support table. Basic circuit components include: reactor segment, NaK to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and a spill reservoir. A 37-pin partial-array core (pin and flow path dimensions are the same as those in a fill design) was selected for fabrication and test. This paper summarizes the integration and preparations for the fill of the pumped liquid metal NaK flow circuit.
Garber, Anne↗
Experimentally Observed Electrical Durability of 4H-SiC JFET ICs Operating from 500 C to 700 C
Prolonged 500 degrees Celsius to 700 degrees Celsius electrical testing data from 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) are combined with post-testing microscopic studies in order to gain more comprehensive understanding of the durability limits of the present version of NASA Glenn's extreme temperature microelectronics technology. The results of this study support the hypothesis that T ≥ 500 degrees Celsius durability-limiting IC failure initiates with thermal-stress-related crack formation where dielectric passivation layers overcoat micron-scale vertical features including patterned metal traces.
high temperature↗
Addressable test matrix for measuring analog transfer characteristics of test elements used for integrated process control and device evaluation
A set of addressable test structures, each of which uses addressing schemes to access individual elements of the structure in a matrix, is used to test the quality of a wafer before integrated circuits produced thereon are diced, packaged and subjected to final testing. The electrical characteristic of each element is checked and compared to the electrical characteristic of all other like elements in the matrix. The effectiveness of the addressable test matrix is in readily analyzing the electrical characteristics of the test elements and in providing diagnostic information.
Buehler, Martin G.↗
Predicting Lifetimes Of CMOS ASIC's From Test Data
Concise report discusses recent developments in use of semiempirical mathematical models to predict rates of failure and operating lifetimes of complementary metal oxide/semiconductor (CMOS) application-specific integrated circuits (ASIC's). Each model represents specific mechanism of failure. Once failure mechanisms and models relevant to given ASIC chosen, adjustable parameters in models fitted to life-test data acquired from representative integrated-circuit structures on test coupons fabricated along with ASIC's. Then design parameters of ASIC's incorporated into models, and models yield lifetimes.
Buehler, Martin G.↗
Solid state television camera
The design, fabrication, and tests of a solid state television camera using a new charge-coupled imaging device are reported. An RCA charge-coupled device arranged in a 512 by 320 format and directly compatible with EIA format standards was the sensor selected. This is a three-phase, sealed surface-channel array that has 163,840 sensor elements, which employs a vertical frame transfer system for image readout. Included are test results of the complete camera system, circuit description and changes to such circuits as a result of integration and test, maintenance and operation section, recommendations to improve the camera system, and a complete set of electrical and mechanical drawing sketches.
Source record↗
Making A D-Latch Sensitive To Alpha Particles
Standard complementary metal oxide/semiconductor (CMOS) D-latch integrated circuit modified to increase susceptibility to single-event upsets (SEU's) (changes in logic state) caused by impacts of energetic alpha particles. Suitable for use in relatively inexpensive bench-scale SEU tests of itself and of related integrated circuits like static random-access memories.
Buehler, Martin G.↗
Generating Weighted Test Patterns for VLSI Chips
Improved built-in self-testing circuitry for very-large-scale integrated (VLSI) digital circuits based on version of weighted-test-pattern-generation concept, in which ones and zeros in pseudorandom test patterns occur with probabilities weighted to enhance detection of certain kinds of faults. Requires fewer test patterns and less computation time and occupies less area on circuit chips. Easy to relate switching activity in outputs with fault-detection activity by use of probabilistic fault-detection techniques.
Siavoshi, Fardad↗
Finding Open Faults In CMOS Circuits
Algorithm specifies sequence of input test signals and interpretation of resulting output signals for identifying stuck-open faults in complementary metal-oxide semiconductor (CMOS) integrated logic circuits. Incorporated in software for online production testing of CMOS circuits.
Chandramouli, R.↗
Superconductive Coplanar-Waveguide Filters
Coplanar-waveguide microwave low-pass filters based on thin films of high-critical-temperature superconductor YBa2Cu3O7 built and tested. Designed to provide passband of 0 to 9.5 GHz. Dimensions suitable for microwave integrated circuits and chosen to provide fairly stringent test of usefulness and practicality of design and of method of fabrication. Insertion loss less than filter made with copper.
Chew, Wilbert↗
System Measures Logic-Gate Delays
Many gates on chip tested automatically. Automatic testing system measures signal-propagation delays of experimental integrated-circuit array of logic gates. Includes controlling computer, counter/time, and feedback-controlled timing-waveform generator. Multiplexer included on integrated-circuit chip with logic-gate array to be tested. Delays measured by system serve as valuable data for design of fast logic and memory chips.
Blaes, Brent R.↗