SEARCH · Search NASA
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
An improved closed-loop controller has been built for a three-axis piezoelectric positioning stage. The stage can be any of a number of commercially available or custom-made units that are used for precise three-axis positioning of optics in astronomical instruments and could be used for precise positioning in diverse fields of endeavor that include adaptive optics, fabrication of semiconductors, and nanotechnology.
Systems, methods and apparatus are provided through which in some embodiments a mass spectrometer micro-leak includes a number of channels fabricated by semiconductor processing tools and that includes a number of inlet holes that provide access to the channels.
A facility that includes a probe station and a scanning open-ended waveguide probe for measuring near electromagnetic fields has been added to Glenn Research Center's suite of antenna-testing facilities, at a small fraction of the cost of the other facilities. This facility is designed specifically for nondestructive characterization of the radiation patterns of miniaturized microwave antennas fabricated on semiconductor and dielectric wafer substrates, including active antennas that are difficult to test in traditional antenna-testing ranges because of fragility, smallness, or severity of DC-bias or test-fixture requirements. By virtue of the simple fact that a greater fraction of radiated power can be captured in a near-field measurement than in a conventional far-field measurement, this near-field facility is convenient for testing miniaturized antennas with low gains.
A method of manufacturing regular arrays of precisely sized, shaped, positioned, and oriented carbon nanotubes has been proposed. Arrays of carbon nanotubes could prove useful in such diverse applications as communications (especially for filtering of signals), biotechnology (for sequencing of DNA and separation of chemicals), and micro- and nanoelectronics (as field emitters and as signal transducers and processors). The method is expected to be suitable for implementation in standard semiconductor-device fabrication facilities.
Systems, methods and apparatus are provided through which in some embodiments a mass spectrometer micro-leak includes a number of channels fabricated by semiconductor processing tools and that includes a number of inlet holes that provide access to the channels.
Gaseous contaminants, such as oxygen and water vapor, are often present in containerless materials processing and in semiconductor device fabrication.
The present technology can be used to control the current injection profile in the longitudinal direction of a high-power diode laser in order to optimize current densities as a function of position in the cavity to promote higher reliable output power and increase the electrical to optical conversion efficiency of the device beyond the level which can be achieved without application of this technique. This approach can be utilized, e.g., in the fabrication of semiconductor laser chips to improve the output power and wall plug efficiency for applications requiring improved performance operation.
The present technology can be used to control the current injection profile in the longitudinal direction of a high-power diode laser in order to optimize current densities as a function of position in the cavity to promote higher reliable output power and increase the electrical to optical conversion efficiency of the device beyond the level which can be achieved without application of this technique. This approach can be utilized, e.g., in the fabrication of semiconductor laser chips to improve the output power and wall plug efficiency for applications requiring improved performance operation.
Fabrication induced surface instabilities in semiconductor devices
A photonic integrated circuit (PIC) includes a semiconductor substrate, one or more passive components, and one or more active components. The one or more passive components are fabricated on the semiconductor substrate, wherein the passive components are fabricated in a III-V type semiconductor layer. The one or more active components are fabricated on top of the one or more passive components, wherein optical signals are communicated between the one or more active components via the one or more passive components.
A photonic integrated circuit (PIC) includes a semiconductor substrate, one or more passive components, and one or more active components. The one or more passive components are fabricated on the semiconductor substrate, wherein the passive components are fabricated in a III-V type semiconductor layer. The one or more active components are fabricated on top of the one or more passive components, wherein optical signals are communicated between the one or more active components via the one or more passive components.
Low-temperature plasmas (LTPs) are essential to manufacturing devices in the semiconductor industry, from creating extreme ultraviolet photons used in the most advanced lithography to thin film etching, deposition, and surface modifications. It is estimated that 40%–45% of all process steps needed to manufacture semiconductor devices use LTPs in one form or another. LTPs have been an enabling technology in the multidecade progression of the shrinking of device dimensions, often referred to as Moore’s law. New challenges in circuit and device design, novel materials, and increasing demands to achieve environmentally benign processing technologies require advances in plasma technology beyond the current state-of-the-art. The Department of Energy Office of Science Fusion Energy Sciences held a workshop titled Plasma Science for Microelectronics Nanofabrication in August 2022 to discuss the plasma science challenges and technical barriers that need to be overcome to continue to develop the innovative plasma technologies required to support and advance the semiconductor industry. One of the key outcomes of the workshop was identifying a set of priority research opportunities (PROs) to focus attention on the most strategic plasma science challenges to address to benefit the semiconductor industry. For each PRO, scientific challenges and recommended strategies to address those challenges were identified. Furthermore, this article summarizes the PROs identified by the workshop participants.
The p-n junction is one of the fundamental requirements for a practical semiconductor-based electronic device. Designing a heterojunction comprising of dissimilar p-type and n-type semiconductors calls for careful energy level considerations, both when selecting the semiconductor materials as well as the metal contacts. A homojunction based on a single semiconductor simplifies this task, as energy levels of the p-type and n-type materials are already fairly similar, allowing for easier selection of contacts. Traditionally, homojunctions rely on doping of a bulk semiconductor to achieve p- and n-type transport through controlled addition of aliovalent dopants via energy-intensive processes such as ion implantation or thermal annealing. Exact control of doping in nanocrystalline semiconductors is significantly more challenging, due to self-purification effects. However, owing to their large surface areas, surface moieties can be utilized to both dope the nanostructures as well as tune their energy levels. Here, we present a facile technique based on an isoelectronic surface dopant in order to achieve p- and n-type materials based on the same semiconductor. We show that thin p-type colloidal Bi 2 Te 3 nanowires can be switched to n-type through surface functionalization, thus increasing the availability of new nanocrystalline solution-processable p-n homojunctions.
The characteristics of the low resistivity diode and the double epitaxial style diode are reported. Both met required breakdown voltage and capacitance voltage characteristics. The double epitaxial style diodes are expected to improve target efficiencies.
Ion implantation is a robust and established method to customize the electronic properties of Si. However, fabricating doped, ultrafine semiconductor nanostructures can be challenging. Ion implantation has well-established effects on the dry etch rates of Si, which becomes increasingly consequential as the target dimension shrinks below a few tens of nanometers. While dry etching arrays of block copolymer-templated nanoscale holes (pitch = 37.5 nm, diameter ~25 nm) into p-type, n-type, and undoped Si, we observed that the lateral etch rate was notably larger for the n-type regions than p-type or undoped regions. By doing image analyses on high resolution electron micrographs of the nanostructured hole arrays, we were able to extract the porosity and average radii of the holes with subnanometer sensitivity and compare the relative etch rates between different doping conditions. We found that degenerately doped n-type silicon consistently etches between approximately 17% and 27% faster in the lateral direction than p-type Si, resulting in significantly larger porosity and, consequently, less mechanical stability. Here, we demonstrate that top-down dimensional analysis of a densely packed porous nanostructure is a robust method for assessing extremely small differences in the lateral, chemical etch rate of doped Si to a degree of sensitivity that was previously unachievable. The minute, dense-packed nature of block copolymer self-assembled nanostructures is shown to be ideal for this application. This proposed method could be useful for designing fabrication processes for heterogeneous nanostructures, as slight dry etch rate variations that may be within process tolerance at the micrometer-scale appear to have nontrivial consequences at the nanometer scale.
Low temperature semiconductor deposition techniques in fabricating thick film, insulated gate, field effect transistors
The method of the invention promotes single crystal growth during fabrication of melt growth semiconductors. A growth ampoule and its tip have a semiconductor source material placed therein. The growth ampoule is placed in a first thermal environment that raises the temperature of the semiconductor source material to its liquidus temperature. The growth ampoule is then transitioned to a second thermal environment that causes the semiconductor source material in the growth ampoule's tip to attain a temperature that is below the semiconductor source material's solidus temperature. The growth ampoule so-transitioned is then mechanically perturbed to induce single crystal growth at the growth ampoule's tip.
Report describes complementary metal-oxide-semiconductor (CMOS) process used to fabricate integrated circuits at Marshall Space Flight Center. It also presents general discussions of circuit design, mask making packaging, and testing.