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At least 127 records · Page 7

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NASA NTRS2017

Integrated Multi-Color Light Emitting Device Made with Hybrid Crystal Structure

An integrated hybrid crystal Light Emitting Diode ("LED") display device that may emit red, green, and blue colors on a single wafer. The various embodiments may provide double-sided hetero crystal growth with hexagonal wurtzite III-Nitride compound semiconductor on one side of (0001) c-plane sapphire media and cubic zinc-blended III-V or II-VI compound semiconductor on the opposite side of c-plane sapphire media. The c-plane sapphire media may be a bulk single crystalline c-plane sapphire wafer, a thin free standing c-plane sapphire layer, or crack-and-bonded c-plane sapphire layer on any substrate. The bandgap energies and lattice constants of the compound semiconductor alloys may be changed by mixing different amounts of ingredients of the same group into the compound semiconductor. The bandgap energy and lattice constant may be engineered by changing the alloy composition within the cubic group IV, group III-V, and group II-VI semiconductors and within the hexagonal III-Nitrides.

Park, Yeonjoon↗

DOE OSTI2023

Pulsed laser ejection of single-crystalline III-V solar cells from GaAs substrates

The best III-V solar cells start out as single-crystalline multilayers on GaAs substrates. Separating these multilayers from their growth substrate enables higher performance and wafer reuse, which are both critical for terrestrial III-V solar cell viability. Here, we remove rigidly bonded, 16 mm 2 x 3.5μm thick devices from a GaAs substrate using an unfocused Nd:YAG laser pulse. The pulse is absorbed by a low-bandgap, lattice-matched layer below the device, driving an ablation event that ejected the crystalline multilayer from the substrate. Minutes of selective wet-chemical etching and device finishing yield a 0.1 cm 2 device with a 17.4% power conversion efficiency and open-circuit voltage of 1.07 V, using AM1.5 direct with no anti-reflection coating. We show that the performance is comparable to similar cells produced via conventional processes. We discuss unique process characteristics, such as the potential to separate wafer-sized solar cells per laser pulse.

14 SOLAR ENERGY↗

NASA NTRS2009

Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays

The silicon substrate carrier was created so that a large-area array (in this case 62,000+ elements of a microshutter array) and a variety of discrete passive and active devices could be mounted on a single board, similar to a printed circuit board. However, the density and number of interconnects far exceeds the capabilities of printed circuit board technology. To overcome this hurdle, a method was developed to fabricate this carrier out of silicon and implement silicon integrated circuit (IC) technology. This method achieves a large number of high-density metal interconnects; a 100-percent yield over a 6-in. (approximately equal to 15-cm) diameter wafer (one unit per wafer); a rigid, thermally compatible structure (all components and operating conditions) to cryogenic temperatures; re-workability and component replaceability, if required; and the ability to precisely cut large-area holes through the substrate. A method that would employ indium bump technology along with wafer-scale integration onto a silicon carrier was also developed. By establishing a silicon-based version of a printed circuit board, the objectives could be met with one solution. The silicon substrate would be 2 mm thick to survive the environmental loads of a launch. More than 2,300 metal traces and over 1,500 individual wire bonds are required. To mate the microshutter array to the silicon substrate, more than 10,000 indium bumps are required. A window was cut in the substrate to allow the light signal to pass through the substrate and reach the microshutter array. The substrate was also the receptacle for multiple unpackaged IC die wire-bonded directly to the substrate (thus conserving space over conventionally packaged die). Unique features of this technology include the implementation of a 2-mmthick silicon wafer to withstand extreme mechanical loads (from a rocket launch); integrated polysilicon resistor heaters directly on the substrate; the precise formation of an open aperture (approximately equal to 3x3cm) without any crack propagation; implementation of IR transmission blocking techniques; and compatibility with indium bump bonding. Although designed for the microshutter arrays for the NIRSpec instrument on the James Webb Space Telescope, these substrates can be linked to microshutter applications in the photomask generation and stepper equipment used to make ICs and microelectromechanical system (MEMS) devices.

Jhabvala, Murzy↗

DOE OSTI2021

Wafer-scale remote epitaxy of III-V semiconductors and applications

In conventional epitaxy of single-crystalline semiconductor materials, it is challenging to separate the grown layer with the substrate due to the strong bonding at the interface. Remote epitaxy is a recently discovered method to grow single-crystalline thin films on graphene, wherein the grown film can be exfoliated at the graphene interface to form freestanding membranes. Here, we present our recent development on remote epitaxy of III-V semiconductors. We show that directly growing 2D materials on III-V substrates as a remote epitaxy template is an ideal pathway that can eliminate transfer process-related defects and can realize wafer-scale process of remote epitaxy and substrate reuse. We present the strategies to grow 2D materials on the surface of III-V materials, which is much more challenging than thermally robust substrates such as SiO2/Si or sapphire. The nucleation of III-V on 2D material-coated III-V platforms via remote interaction is investigated both experimentally and theoretically. Lastly, we show advanced remote epitaxial platforms and optoelectronic applications enabled by remote epitaxy, and the capability to recycle the III-V substrates for repeated remote epitaxy and production of freestanding III-V thin films.

Kim, Hyunseok↗

DOE OSTI2021

Wafer-scale remote epitaxy of III-V semiconductors and applications

Kim, Hyunseok↗

NASA NTRS2012

Bump Bonding Using Metal-Coated Carbon Nanotubes

Bump bonding hybridization techniques use arrays of indium bumps to electrically and mechanically join two chips together. Surface-tension issues limit bump sizes to roughly as wide as they are high. Pitches are limited to 50 microns with bumps only 8-14 microns high on each wafer. A new process uses oriented carbon nanotubes (CNTs) with a metal (indium) in a wicking process using capillary actions to increase the aspect ratio and pitch density of the connections for bump bonding hybridizations. It merges the properties of the CNTs and the metal bumps, providing enhanced material performance parameters. By merging the bumps with narrow and long CNTs oriented in the vertical direction, higher aspect ratios can be obtained if the metal can be made to wick. Possible aspect ratios increase from 1:1 to 20:1 for most applications, and to 100:1 for some applications. Possible pitch density increases of a factor of 10 are possible. Standard capillary theory would not normally allow indium or most other metals to be drawn into the oriented CNTs, because they are non-wetting. However, capillary action can be induced through the ability to fabricate oriented CNT bundles to desired spacings, and the use of deposition techniques and temperature to control the size and mobility of the liquid metal streams and associated reservoirs. This hybridization of two technologies (indium bumps and CNTs) may also provide for some additional benefits such as improved thermal management and possible current density increases.

Lamb, James L.↗

DOE OSTI2026

Epitaxy of Beta-Ga2O3 on Highly-Offcut (Greater than 10 Degrees) Substrates

Beta-Ga2O3 has emerged as a leading candidate for next-generation power electronics, radio frequency (RF) switches, and extreme environment electronics due to a wide band gap (4.6 - 4.9 eV), high dopability (approximately 40 meV activation energy for an isolated silicon donor), and melt growth characteristics resulting in commercially available 4-inch substrates and commercial demonstrations of 6-inch substrates by multiple techniques. The (100) surface of Ga2O3 is highly desirable from a device and epitaxy standpoint - bulk growth of (100) material is more scalable than (010), the surface is nearly lattice-matched to p-type partner NiO, and Al2O3 incorporates at higher concentrations without phase separation. However, the epitaxial growth rate on (100) surfaces is less than 10% of other faces due to weak bonding and favorable desorption. Recent demonstrations have shown growth rate improvements from 0.4 nm/min to 1.5 nm/min by growing on (100) wafers that are offcut 6 degrees in the -c direction.1 These films show step-flow growth from (-201) step-edges and high electron mobility. Despite these exciting results, offcuts greater than 6 degrees have not been explored due to the waste associated with grinding and polishing large offcuts. In this talk we will discuss the molecular beam epitaxy (MBE) growth and properties of Beta-Ga2O3 grown on (100) substrates offcut in the -c direction up to 13.4 degrees. These large offcuts are enabled by edge-fed film-defined growth (EFG) where the offcut is grown into the surface by pulling the crystal through the EFG die with the seed crystal rotated by the desired offcut angle. We will demonstrate that 13.4 degrees offcut substrates still exhibit a terraced (100) surface, and that a >10x increase (4.8 nm/min) in growth rate is achieved. As previously reported on lower offcuts, we observe 100% reversal of substrate twin domains around the (001) direction at the substrate-epilayer interface. We will discuss electrical properties including record-low (by MBE) unintentional doping densities of < 5E15 cm-3.

36 MATERIALS SCIENCE↗

NASA NTRS2004

High-Temperature Probe Station Developed to Characterize Microwave Devices Through 500 C

A photograph and a block diagram of the high-temperature probe station are shown. The system consists of the ceramic heater mounted on a NASA shuttle tile insulator, a direct current power supply, a personal-computer-based data acquisition and temperature controller, microwave probes, a microscope, and a network analyzer. The ability to perform microwave tests at high temperatures is becoming necessary. There is now a need for sensors and communication circuits that can operate at 500 C and above for aircraft engine development and monitoring during flight. To address this need, researchers have fabricated devices using wide bandgap semiconductors such as SiC with targeted operating temperatures of 500 to 600 C. However, the microwave properties of these devices often change drastically with temperature, so any designs that are intended to be used in such an environment must be characterized at high temperatures. For some reliability, lifetime, and direct-current testing, the device under test can be packaged and characterized in an oven. However, for RF and microwave measurements, it is usually not possible to establish a calibrated reference plane at the device terminals within a package. In addition, the characteristics of the package would vary over a 500 C temperature range, and this would have to be accounted for when the data were analyzed. A high temperature probe station allows circuits and devices to be characterized through on wafer measurements across a broad temperature range with known reference plane. The conventional, commercially available thermal wafer-probe stations that are used to evaluate microwave devices across a controlled temperature range have a typical upper limit of 200 C. Standalone thermal heating chucks are available with an extended upper temperature range of 300 to 400 C. To effectively characterize devices at temperatures up to and surpassing 500 C, Glenn researchers developed a custom probe station. In the past, custom probe stations have been developed to test devices under other extreme environments, such as cryogenic temperatures as low as 37 K. Similarly, this custom probe station was specifically modified for high-temperature use. It allows devices to be measured quickly and flexibly, without the use of wire bonds and test fixtures. The probe station is shown making scattering parameter measurements from 1 to 50 GHz with a Hewlett-Packard 8510C Network Analyzer. There is a half-wafer of silicon directly on top of the heater to provide a uniform heated platform for our sample. A quarter wafer of silicon carbide forms the substrate for our test circuit of several transmission lines.

Downey, Alan N.↗

NASA NTRS1984

Structurally stable, thin silicon solar cells

A fabrication process for structurally stable thin solar cell wafers that produce good power output after irradiation is described. The fabrication process is as follows. A 6 mil, circular wafer is oxidized on both sides. One side is then patterned with a rectangular array of holes in the oxide that are nominally 75 mils square and separated by 2 mil spacings. Wells are then etched into the silicon with KOH to a depth of 4 mils, leaving a 2 mil, unetched thickness. Two areas on the surface are left unetched to provide pads for bonding or testing. All oxide is then removed and the rest of the processing is normal; the unetched face is used as the illuminated face. When all other processing is complete, a 2 X 2 cm cell is sawed from the starting wafer leaving a border that is approximately 10 mils wide. The effective thickness, determined by weighing an unmetallized sample, of such a cell is about 2.4 mil.

Arndt, R. A.↗

DOE OSTI2025

Silylsilane‐Substituted Polymers: Fluorine‐Free, Liquid Repellent, and Hydrolytically Stable Alternatives to Siloxanes

Abstract Per‐ and polyfluoroalkyl substances (PFAS) are omniphobic and exceptionally stable, making them ideal for a wide range of materials applications. However, as “forever chemicals”, their exceptional persistence and bioaccumulation have generated an increasing amount of environmental and health concerns, prompting the search for fluorine‐free alternatives. Siloxane‐based materials are therefore interesting to examine as PFAS alternatives due to their low surface energy and hydrophobicity but suffer from hydrolytic instability of Si─O linkages. To address this challenge, a novel methacrylate monomer, 3‐[tris(trimethylsilyl)silyl]propyl methacrylate (M‐silyl), is designed containing Si─Si bonds rather than Si─O bonds of siloxanes. Polymers derived from M‐silyl (P‐silyl) is prepared by controlled free radical polymerization and compared with their siloxane analogues after coating on silicon wafers. Contact angle (CA) measurements confirmed P‐silyl to be hydrophobic (advancing/receding water CA = 109.7°/83.0°), with a low‐hysteresis for oil (lyophobic) (hexadecane CA hysteresis = 2.0°), comparable to its siloxane‐based counterpart. Importantly, P‐silyl maintained these surface properties after exposure to acidic or basic conditions, while siloxane analogues lost hydrophobicity. Consequently, the incorporation of Si ─ Si linkages into the design of the polymer enables chemically stable, fluorine‐free alternatives for water‐repellent and low hysteresis surface coatings and advances the design of fluorine‐free functional materials.

fluorine-free↗

DOE OSTI2021

Thin-Entrance Window Process for Soft X-Ray Sensors

New free electron lasers, such as SLAC’s LCLS-II, will provide unique scientific imaging opportunities. In order to fully utilize these facilities, we need to develop detectors with shallow entrance windows that will enable detection of soft x-rays from 250 eV to 1.5 KeV. Achieving adequately shallow entrance windows is challenging because the high temperature anneal needed to activate the dopant also drives the dopant profile deeper, growing the region that is insensitive to soft x-rays. A new microwave annealing technology provides an efficient way to achieve shallow entrance windows in fully depleted high-resistivity silicon sensors. The microwave anneal technique can activate dopants at low substrate temperature, with minimal dopant diffusion, and can be used to fabricate both n-type and p-type entrance windows. SRP and SIMS measurements were used to verify dopant activation with negligible dopant diffusion. We then applied the microwave anneal process to a planar sensor wafer, using the new process to create the backside diode contact. Electrical test of the resulting sensors shows good reverse bias characteristics. The sensors have been bump-bonded to a read-out ASIC and used successfully to measure an Fe-55 x-ray spectrum. Process and device simulations were performed to characterize the quantum efficiency of the entrance window for soft x-rays. This technique is useful for other sensor applications requiring a shallow entrance window, including detectors for UV photons, low energy ions and low energy electrons.

47 OTHER INSTRUMENTATION↗

DOE OSTI2022

Room Temperature, Dip Coating Organic Passivation for c-Si Surfaces

Surface passivation of crystalline Si (c-Si) to reduce recombination rate is crucial to obtain high-efficiency c-Si solar cells. A fast passivation technique that can be performed at room temperature is needed when studying the degradation behaviors using various characterization methods to not destroy the degraded states. In this contribution, we explore Nafion via dip coating on n-type Cz wafers. We show that both the Nafion concentration and the conditions of surface and edge affect the passivation quality, and we achieve excellent passivation quality of iVoc of 716 mV, with a saturation current density (J0) of 7 fA/cm2. Additionally, electron paramagnetic resonance (EPR) shows Nafion can be used under cryogenic temperature and reveals the reduction of Si dangling bond after Nafion treatment.

dielectric solar cell↗

NASA NTRS1984

Interfacial bonding stability

Interfacial bonding stability by in situ ellipsometry was investigated. It is found that: (1) gamma MPS is an effective primer for bonding ethylene vinyl acetate (EVA) to aluminum; (2) ellipsometry is an effective in situ technique for monitoring the stability of polymer/metal interfaces; (3) the aluminized back surface of silicon wafers contain significant amounts of silicon and may have glass like properties.

Boerio, J.↗

DOE OSTI2026

Fast Growth of Ga2O3 on Highly Offcut (100)-Oriented Substrates

Beta-Ga2O3 has emerged as a leading candidate for next-generation power electronics, radio frequency (RF) switches, and extreme environment electronics due to a wide band gap (4.6 - 4.9 eV), high dopability (approximately 40 meV activation energy for an isolated silicon donor), and melt growth characteristics resulting in commercially available 4-inch substrates and commercial demonstrations of 6-inch substrates by multiple techniques. The (100) surface of Ga2O3 is highly desirable from a device and epitaxy standpoint - bulk growth of (100) material is more scalable than (010), the surface is nearly lattice-matched to p-type partner NiO, and Al2O3 incorporates at higher concentrations without phase separation. More importantly, the impact ionization coefficients along the [100] direction are low, leading to the highest possible critical fields. This is advantageous compared to the current state of the art, (001), due to reduced surface defects and increased possible breakdown voltage. However, the epitaxial growth rate on (100) surfaces is less than 10% of other faces due to weak bonding and favorable desorption, and on-axis (100) growth easily forms twin domains. Recent demonstrations have shown growth rate improvements from 0.4 nm/min to 1.5 nm/min by growing on (100) wafers that are offcut 6 degrees in the -c direction. These films show step-flow growth from (20-1) step-edges and high electron mobility due to suppressed twins. Despite these exciting results, offcuts greater than 6 degrees have not been explored due to the waste associated with grinding and polishing large offcuts. In this talk we will discuss the molecular beam epitaxy (MBE) growth and properties of Beta-Ga2O3 grown on (100) substrates offcut in the -c direction up to 13.4 degrees. These large offcuts are enabled by edge-fed film-defined growth (EFG) where the offcut is grown into the surface by pulling the crystal through the EFG die with the seed crystal rotated by the desired offcut angle. We will demonstrate that 13.4 degrees offcut substrates still exhibit a terraced (100) surface, and that a >10x increase (>5 nm/min) in growth rate is achieved. As previously reported on lower offcuts, we observe reversal of substrate twin domains around the (001) direction at the substrate-epilayer interface. We will discuss electrical properties including record-low (by MBE) unintentional doping densities of < 5E15 cm-3 and critical breakdown field in Schottky barrier diodes comparable with state-of-the-art (001) Ga2O3 without edge termination.

36 MATERIALS SCIENCE↗

DOE OSTI2023

Micro-Transfer Printing of Repeaters on Passive Interposer

Silicon-based sensors are central to particle physics experiments and particle tracking detectors. New-generation Large Focal Plane Arrays (LFPAs) cover areas that extend beyond several square meters. Distributing power and transporting data across such areas while maintaining good signal integrity is a complicated challenge. Tiling the detector on an organic interposer would be far too expensive and take too much space while offering little to no advantage regarding signal integrity. Passive silicon interposers are much less expensive and more integrable but would worsen signal integrity because of their inherent higher dielectric constant. Active interposers are a good compromise from the economic and signal integrity standpoint; unfortunately, their yield trends to zero for areas greater than a reticle size, making this technology incompatible with our application. NHanced proposes to duplicate the behavior of a high-yield, low-cost active interposer by printing active microcomponents on a passive interposer with our die-to-wafer micro-transfer printing (MTP) technology. This resolves the signal integrity and power distribution limitations. In Phase I, we designed and simulated analog and digital repeaters to be MTPed onto a passive silicon interposer test wafer.

2.5D↗

DOE OSTI2020

Sulfurization as a promising surface passivation approach for both n- and p-type Si

Sulfur is shown to be an effective and promising surface passivation element for both n- and p-type Si wafers after reacting in dilute hydrogen sulfide gas (2 - 6% in argon) at 550°C. Effective minority carrier lifetimes of > 2 ms and > 0.25 ms are achieved for n- and p-type Si wafers, respectively, comparable to the industry standard thermal oxide and atomic layer deposited aluminum oxide passivation level. Surface characterization by x-ray photoelectron and emission spectroscopy reveals that sulfur is primarily bonded in a sulfide environment.

42 ENGINEERING↗

DOE OSTI2024

Silicon-On-Silicon Carbide Platform for Integrated Photonics

Silicon carbide (SiC)'s nonlinear optical properties and applications to quantum information have recently brought attention to its potential as an integrated photonics platform. However, despite its many excellent material properties, such as large thermal conductivity, wide transparency window, and strong optical nonlinearities, it is generally a difficult material for microfabrication. Here, it is shown that directly bonded silicon-on-silicon carbide can be a high-performing hybrid photonics platform that does not require the need to form SiC membranes or directly pattern in SiC. The optimized bonding method yields defect-free, uniform films with minimal oxide at the silicon–silicon–carbide interface. Ring resonators are patterned into the silicon layer with standard, complimentary metal–oxide–semiconductor (CMOS) compatible (Si) fabrication and measure room-temperature, near-infrared quality factors exceeding 10 5 . The corresponding propagation loss is 5.7 dB cm -1 . The process offers a wafer-scalable pathway to the integration of SiC photonics into CMOS devices.

36 MATERIALS SCIENCE↗

DOE OSTI2024

Treatment and aging studies of GaAs(111)B substrates for van der Waals chalcogenide film growth

GaAs(111)B are commercially available substrates widely used for the growth of van der Waals chalcogenide films. Wafer-scale, high-quality crystalline films can be deposited on GaAs(111)B substrates using molecular beam epitaxy. However, two obstacles persist in the use of GaAs(111)B: first, the surface dangling bonds make it challenging for the growth of van der Waals materials; second, the As-terminated surface is prone to aging in air. This study investigated a thermal treatment method for deoxidizing GaAs(111)B substrates while simultaneously passivating the surface dangling bonds with Se. By optimizing the treatment parameters, we obtained a flat and completely deoxidized platform for subsequent film growth, with highly reproducible operations. Furthermore, through first-principle calculations, we find that the most energetically favorable surface of GaAs(111)B after Se passivation consists of 25% As atoms and 75% Se atoms. Finally, we discovered that the common storage method using food-grade vacuum packaging cannot completely prevent substrate aging, and even after thermal treatment, aging still affects subsequent growth. Therefore, we recommend using N2-purged containers for better preservation.

Engineering↗