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NASA NTRS2001

Electronics for Extreme Environments

Most of the NASA missions involve extreme environments comprising radiation and low or high temperatures. Current practice of providing friendly ambient operating environment to electronics costs considerable power and mass (for shielding). Immediate missions such as the Europa orbiter and lander and Mars landers require the electronics to perform reliably in extreme conditions during the most critical part of the mission. Some other missions planned in the future also involve substantial surface activity in terms of measurements, sample collection, penetration through ice and crust and the analysis of samples. Thus it is extremely critical to develop electronics that could reliably operate under extreme space environments. Silicon On Insulator (SOI) technology is an extremely attractive candidate for NASA's future low power and high speed electronic systems because it offers increased transconductance, decreased sub-threshold slope, reduced short channel effects, elimination of kink effect, enhanced low field mobility, and immunity from radiation induced latch-up. A common belief that semiconductor devices function better at low temperatures is generally true for bulk devices but it does not hold true for deep sub-micron SOI CMOS devices with microscopic device features of 0.25 micrometers and smaller. Various temperature sensitive device parameters and device characteristics have recently been reported in the literature. Behavior of state of the art technology devices under such conditions needs to be evaluated in order to determine possible modifications in the device design for better performance and survivability under extreme environments. Here, we present a unique approach of developing electronics for extreme environments to benefit future NASA missions as described above. This will also benefit other long transit/life time missions such as the solar sail and planetary outposts in which electronics is out open in the unshielded space at the ambient space temperatures and always exposed to radiation. Additional information is contained in the original extended abstract.

Patel, J. U.↗

NASA NTRS2005

Overview of Results from the Cassini Magnetospheric Imaging Instrument (MIMI) During the First Year of Operations

The MIMI investigation comprises three sensors covering the indicated energy ranges: the Ion and Neutral Camera (INCA) -- 7 keV/nuc 3 Mev) and protons (1.6 < E < 160 Mev) from the back end of the dual field-of-view telescope. The Saturn observation sequences began in January, 2004 and culminated in Saturn Orbit Insertion on July 1, 2004. The MIMI sensors observed substantial activity in interplanetary space for several months prior to SOI, including several interplanetary shocks associated with corotating interaction regions, numerous increases most likely originating from particle streams in the vicinity of the Saturnian bow shock and energetic neutral atoms (ENA) emanating from Saturn s magnetosphere. Results following SOI revealed: a dynamical magnetosphere with a day-night asymmetry and an 11-hour periodicity; several water-product ions (O+, OH+, H2O+), but little N+; inferred quantities of neutral gas sufficient to cause major losses in the trapped ions and electrons in the middle and inner magnetosphere; a Titan exosphere that is a copious source of ENA; INCA imaging through ENA has also revealed a previously unknown radiation belt residing inward of the D-ring that is most likely the result of double charge-exchange between the main radiation belt and the upper layers of Saturn s exosphere. Finally, there is ample evidence for the presence of substorm-like injections of plasma that subsequently corotates for a number of days before dissipating on the night-side magnetotail. The observations will be presented and discussed in the context of current theoretical models.

Krimigis, S. M.↗

NASA NTRS2005

Cassini CIRS Observations of Saturn's Rings

In the spring of 2004, during Cassini s approach to Saturn, the Cassini Composite Infrared Spectrometer (CIRS) began acquiring thermal spectra of Saturn s rings. CIRS is a Fourier-transform spectrometer that measures radiation in the thermal infrared from 7 microns to 1 millimeter (1400 to 10/cm). CIRS has a set of 21 detectors, consisting of two 1 x 10 linear arrays with a pixel size of 0.3 mrad, and one 4 mrad circular detector. Just after the completion of the Saturn orbit insertion (SOI) burn, CIRS performed an especially high spatial resolution scan of portions of Saturn s A, B and C rings. In the months following SOI, additional ring measurements have been obtained, including radial scans on the lit and unlit sides of the rings, and azimuthal scans across the shadowed regions of the A, B and C rings.

Spilker, Linda J.↗

NASA NTRS1998

Buried Oxide Densification for Low Power, Low Voltage CMOS Applications

Special technology and circuit architecture are of growing interest for implementation of circuits which operate at low supply voltages and consume low power levels without sacrificing performance[1]. Use of thin buried oxide SOI substrates is a primary approach to simultaneously achieve these goals. A significant aspect regarding SIMOX SOI for low voltage, low power applications is the reliability and performance of the thin buried oxide. In addition, when subjected to high total dose irradiation, the silicon islands within the BOX layer of SIMOX can store charges and significantly effect the back channel threshold voltages of devices. Thus, elimination of the islands within the buried oxide (BOX) layer is preferred in order to prevent leakage through these conductive islands and charge build-up within the buried oxide layer. A differential (2-step) ramp rate as applied to full and 100 nm BOX SIMOX was previously reported to play a significant role in the stoichiometry and island formation within the buried layer[2]. This paper focus is on the properties of a thin (120nm) buried oxide as a function of the anneal ramp rate and the temperature of anneal. In this research, we have found an improvement in the buried oxide stoichiometry with the use of a slower, singular ramp rate for specified thin buried oxides, with slower ramp rates and higher temperatures of anneal suggested for reducing the presence of Si islands within the BOX layer.

Allen, L. P.↗

NASA NTRS2004

Frequency Dependence of Single-event Upset in Advanced Commerical PowerPC Microprocessors

This paper examines single-event upsets in advanced commercial SOI microprocessors in a dynamic mode, studying SEU sensitivity of General Purpose Registers (GPRs) with clock frequency. Results are presented for SOI processors with feature sizes of 0.18 microns and two different core voltages. Single-event upset from heavy ions is measured for advanced commercial microprocessors in a dynamic mode with clock frequency up to 1GHz. Frequency and core voltage dependence of single-event upsets in registers is discussed.

single-event upset (SEU)↗

NASA NTRS2008

Evaluation of Silicon-on-Insulator HTOP-01 Operational Amplifier for Wide Temperature Operation

Electronics capable of operation under extreme temperatures are required in many of NASA space exploration missions. Aerospace and military applications, as well as some terrestrial industries constitute environments where electronic systems are anticipated to be exposed to extreme temperatures and wide-range thermal swings. Electronics that are able to withstand and operate efficiently in such harsh environments would simplify, if not eliminate, traditional thermal control elements and their associated structures for proper ambient operation. As a result, overall system mass would be reduced, design would be simplified, and reliability would be improved. Electronic parts that are built utilizing silicon-on-insulator (SOI) technology are known to offer better radiation-tolerance compared to their conventional silicon counterparts, provide faster switching, and consume less power. They also exhibit reduced leakage current and, thus, they are often tailored for high temperature operation. These attributes make SOI-based devices suitable for use in harsh environments where extreme temperatures and wide thermal swings are anticipated. A new operational amplifier, based on silicon-on-insulator technology and geared for high temperature well-logging applications, was recently introduced by Honeywell Corporation. This HTOP-01 dual precision operational amplifier is a low power device, operates on a single supply, and has an internal oscillator and an external clocking option [1]. It is rated for operation from -55 C to +225 C with a maximum output current capability of 50 mA. The amplifier chip is designed as a 14-pin, hermetically-sealed device in a ceramic package. Table I shows some of the device manufacturer s specifications.

Patterson, Richard↗

NASA NTRS2008

Update on Development of SiC Multi-Chip Power Modules

Progress has been made in a continuing effort to develop multi-chip power modules (SiC MCPMs). This effort at an earlier stage was reported in 'SiC Multi-Chip Power Modules as Power-System Building Blocks' (LEW-18008-1), NASA Tech Briefs, Vol. 31, No. 2 (February 2007), page 28. The following recapitulation of information from the cited prior article is prerequisite to a meaningful summary of the progress made since then: 1) SiC MCPMs are, more specifically, electronic power-supply modules containing multiple silicon carbide power integrated-circuit chips and silicon-on-insulator (SOI) control integrated-circuit chips. SiC MCPMs are being developed as building blocks of advanced expandable, reconfigurable, fault-tolerant power-supply systems. Exploiting the ability of SiC semiconductor devices to operate at temperatures, breakdown voltages, and current densities significantly greater than those of conventional Si devices, the designs of SiC MCPMs and of systems comprising multiple SiC MCPMs are expected to afford a greater degree of miniaturization through stacking of modules with reduced requirements for heat sinking; 2) The stacked SiC MCPMs in a given system can be electrically connected in series, parallel, or a series/parallel combination to increase the overall power-handling capability of the system. In addition to power connections, the modules have communication connections. The SOI controllers in the modules communicate with each other as nodes of a decentralized control network, in which no single controller exerts overall command of the system. Control functions effected via the network include synchronization of switching of power devices and rapid reconfiguration of power connections to enable the power system to continue to supply power to a load in the event of failure of one of the modules; and, 3) In addition to serving as building blocks of reliable power-supply systems, SiC MCPMs could be augmented with external control circuitry to make them perform additional power-handling functions as needed for specific applications. Because identical SiC MCPM building blocks could be utilized in such a variety of ways, the cost and difficulty of designing new, highly reliable power systems would be reduced considerably. This concludes the information from the cited prior article. The main activity since the previously reported stage of development was the design, fabrication, and testing a 120- VDC-to-28-VDC modular power-converter system composed of eight SiC MCPMs in a 4 (parallel)-by-2 (series) matrix configuration, with normally-off controllable power switches. The SiC MCPM power modules include closed-loop control subsystems and are capable of operating at high power density or high temperature. The system was tested under various configurations, load conditions, load-transient conditions, and failure-recovery conditions. Planned future work includes refinement of the demonstrated modular system concept and development of a new converter hardware topology that would enable sharing of currents without the need for communication among modules. Toward these ends, it is also planned to develop a new converter control algorithm that would provide for improved sharing of current and power under all conditions, and to implement advanced packaging concepts that would enable operation at higher power density.

Lostetter, Alexander↗

NASA NTRS2008

Nano-Multiplication-Region Avalanche Photodiodes and Arrays

Nano-multiplication-region avalanche photodiodes (NAPDs), and imaging arrays of NAPDs integrated with complementary metal oxide/semiconductor (CMOS) active-pixel-sensor integrated circuitry, are being developed for applications in which there are requirements for high-sensitivity (including photoncounting) detection and imaging at wavelengths from about 250 to 950 nm. With respect to sensitivity and to such other characteristics as speed, geometric array format, radiation hardness, power demand of associated circuitry, size, weight, and robustness, NAPDs and arrays thereof are expected to be superior to prior photodetectors and arrays including CMOS active-pixel sensors (APSs), charge-coupled devices (CCDs), traditional APDs, and microchannelplate/ CCD combinations. Figure 1 depicts a conceptual NAPD array, integrated with APS circuitry, fabricated on a thick silicon-on-insulator wafer (SOI). Figure 2 presents selected aspects of the structure of a typical single pixel, which would include a metal oxide/semiconductor field-effect transistor (MOSFET) integrated with the NAPD. The NAPDs would reside in silicon islands formed on the buried oxide (BOX) layer of the SOI wafer. The silicon islands would be surrounded by oxide-filled insulation trenches, which, together with the BOX layer, would constitute an oxide embedding structure. There would be two kinds of silicon islands: NAPD islands for the NAPDs and MOSFET islands for in-pixel and global CMOS circuits. Typically, the silicon islands would be made between 5 and 10 m thick, but, if necessary, the thickness could be chosen outside this range. The side walls of the silicon islands would be heavily doped with electron-acceptor impurities (p+-doped) to form anodes for the photodiodes and guard layers for the MOSFETs. A nanoscale reach-through structure at the front (top in the figures) central position of each NAPD island would contain the APD multiplication region. Typically, the reach-through structure would be about 0.1 microns in diameter and between 0.3 and 0.4 nm high. The top layer in the reach-through structure would be heavily doped with electron-donor impurities (n+-doped) to make it act as a cathode. A layer beneath the cathode, between 0.1 and 0.2 nm thick, would be p-doped to a concentration .10(exp 17)cu cm. A thin n+-doped polysilicon pad would be formed on the top of the cathode to protect the cathode against erosion during a metal-silicon alloying step that would be part of the process of fabricating the array.

Zheng, Xinyu↗

NASA NTRS2009

Improved Starting Materials for Back-Illuminated Imagers

An improved type of starting materials for the fabrication of silicon-based imaging integrated circuits that include back-illuminated photodetectors has been conceived, and a process for making these starting materials is undergoing development. These materials are intended to enable reductions in dark currents and increases in quantum efficiencies, relative to those of comparable imagers made from prior silicon-on-insulator (SOI) starting materials. Some background information is prerequisite to a meaningful description of the improved starting materials and process. A prior SOI starting material, depicted in the upper part the figure, includes: a) A device layer on the front side, typically between 2 and 20 m thick, made of p-doped silicon (that is, silicon lightly doped with an electron acceptor, which is typically boron); b) A buried oxide (BOX) layer (that is, a buried layer of oxidized silicon) between 0.2 and 0.5 m thick; and c) A silicon handle layer (also known as a handle wafer) on the back side, between about 600 and 650 m thick. After fabrication of the imager circuitry in and on the device layer, the handle wafer is etched away, the BOX layer acting as an etch stop. In subsequent operation of the imager, light enters from the back, through the BOX layer. The advantages of back illumination over front illumination have been discussed in prior NASA Tech Briefs articles.

Pain, Bedabrata↗

NASA NTRS2009

Wide-Range Temperature Sensors with High-Level Pulse Train Output

Two types of temperature sensors have been developed for wide-range temperature applications. The two sensors measure temperature in the range of -190 to +200 C and utilize a thin-film platinum RTD (resistance temperature detector) as the temperature-sensing element. Other parts used in the fabrication of these sensors include NPO (negative-positive- zero) type ceramic capacitors for timing, thermally-stable film or wirewound resistors, and high-temperature circuit boards and solder. The first type of temperature sensor is a relaxation oscillator circuit using an SOI (silicon-on-insulator) operational amplifier as a comparator. The output is a pulse train with a period that is roughly proportional to the temperature being measured. The voltage level of the pulse train is high-level, for example 10 V. The high-level output makes the sensor less sensitive to noise or electromagnetic interference. The output can be read by a frequency or period meter and then converted into a temperature reading. The second type of temperature sensor is made up of various types of multivibrator circuits using an SOI type 555 timer and the passive components mentioned above. Three configurations have been developed that were based on the technique of charging and discharging a capacitor through a resistive element to create a train of pulses governed by the capacitor-resistor time constant. Both types of sensors, which operated successfully over the wide temperature range, have potential use in extreme temperature environments including jet engines and space exploration missions.

Hammoud, Ahmad↗

NASA NTRS2009

G(sup 4)FET Implementations of Some Logic Circuits

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

Mojarradi, Mohammad↗

NASA NTRS2007

Wide-Temperature-Range Integrated Operational Amplifier

A document discusses a silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) integrated- circuit operational amplifier to be replicated and incorporated into sensor and actuator systems of Mars-explorer robots. This amplifier is designed to function at a supply potential less than or equal to 5.5 V, at any temperature from -180 to +120 C. The design is implemented on a commercial radiation-hard SOI CMOS process rated for a supply potential of less than or equal to 3.6 V and temperatures from -55 to +110 C. The design incorporates several innovations to achieve this, the main ones being the following: NMOS transistor channel lengths below 1 m are generally not used because research showed that this change could reduce the adverse effect of hot carrier injection on the lifetimes of transistors at low temperatures. To enable the amplifier to withstand the 5.5-V supply potential, a circuit topology including cascade devices, clamping devices, and dynamic voltage biasing was adopted so that no individual transistor would be exposed to more than 3.6 V. To minimize undesired variations in performance over the temperature range, the transistors in the amplifier are biased by circuitry that maintains a constant inversion coefficient over the temperature range.

Mojarradi, Mohammad↗

NASA NTRS2007

G4-FETs as Universal and Programmable Logic Gates

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Johnson, Travis↗

NASA NTRS2010

Method and Circuit for In-Situ Health Monitoring of Solar Cells in Space

This innovation represents a method and circuit realization of a system designed to make in-situ measurements of test solar-cell operational parameters on orbit using readily available high-temperature and high-ionizing-radiation- tolerant electronic components. This innovation enables on-orbit in-situ solar-array health monitoring and is in response to a need recognized by the U.S. Air Force for future solar arrays for unmanned spacecraft. This system can also be constructed out of commercial-grade electronics and can be embedded into terrestrial solar power system as a diagnostics instrument. This innovation represents a novel approach to I-V curve measurement that is radiation and temperature hard, consumes very few system resources, is economical, and utilizes commercially available components. The circuit will also operate at temperatures as low as 55 C and up to +225 C, allowing it to reside close to the array in direct sunlight. It uses a swept mode transistor functioning as a resistive load while utilizing the solar cells themselves as the biasing device, so the size of the instrument is small and there is no danger of over-driving the cells. Further, this innovation utilizes nearly universal spacecraft bus resources and therefore can be readily adapted to any spacecraft bus allowing for ease of retrofit, or designed into new systems without requiring the addition of infrastructure. One unique characteristic of this innovation is that it effects the measurement of I-V curves without the use of large resistor arrays or active current sources normally used to characterize cells. A single transistor is used as a variable resistive load across the cell. This multi-measurement instrument was constructed using operational amplifiers, analog switches, voltage regulators, MOSFETs, resistors, and capacitors. The operational amplifiers, analog switches, and voltage regulators are silicon-on-insulator (SOI) technology known for its hardness to the effects of ionizing radiation. The SOI components used can tolerate temperatures up to 225 C, which gives plenty of thermal headroom allowing this circuit to perhaps reside in the solar cell panel itself where temperatures can reach over 100 C.

Krasowski, Michael J.↗

NASA NTRS2011

Rotation Rate of Saturn's Magnetosphere using CAPS Plasma Measurements

We present the present status of an investigation of the rotation rate of Saturn's magnetosphere using a 3D velocity moment technique being developed at Goddard which is similar to the 2D version used by Sittler et al. for SOI and similar to that used by Thomsen et al.. This technique allows one to nearly cover the full energy range of the Cassini Plasma Spectrometer (CAPS) IMS from 1 V . E/Q < 50 kV. Since our technique maps the observations into a local inertial frame, it does work during roll maneuvers. We make comparisons with the bi-Maxwellian fitting technique developed by Wilson et al. and the similar velocity moment technique by Thomsen et al. . We concentrate our analysis when ion composition data is available, which is used to weight the non-compositional data, referred to as singles data, to separate H+, H2+ and water group ions (W+) from each other. The chosen periods have high enough telemetry rates (4 kbps or higher) so that coincidence ion data, similar to that used by Sittler et al. for SOI is available. The ion data set is especially valuable for measuring flow velocities for protons, which are more difficult to derive using singles data within the inner magnetosphere, where the signal is dominated by heavy ions (i.e., proton peak merges with W+ peak as low energy shoulder). Our technique uses a flux function, which is zero in the proper plasma flow frame, to estimate fluid parameter uncertainties. The comparisons investigate the experimental errors and potential for systematic errors in the analyses, including ours. The rolls provide the best data set when it comes to getting 4PI coverage of the plasma but are more susceptible to time aliasing effects. In the future we will then make comparisons with magnetic field observations, Saturn ionosphere conductivities as presently known and the field aligned currents necessary for the planet to enforce corotation of the rotating plasma.

Sittler, E.↗

NASA NTRS2016

500 C Electronic Packaging and Dielectric Materials for High Temperature Applications

High-temperature environment operable sensors and electronics are required for exploring the inner solar planets and distributed control of next generation aeronautical engines. Various silicon carbide (SiC) high temperature sensors, actuators, and electronics have been demonstrated at and above 500C. A compatible packaging system is essential for long-term testing and application of high temperature electronics and sensors. High temperature passive components are also necessary for high temperature electronic systems. This talk will discuss ceramic packaging systems developed for high temperature electronics, and related testing results of SiC circuits at 500C and silicon-on-insulator (SOI) integrated circuits at temperatures beyond commercial limit facilitated by these high temperature packaging technologies. Dielectric materials for high temperature multilayers capacitors will also be discussed. High-temperature environment operable sensors and electronics are required for probing the inner solar planets and distributed control of next generation aeronautical engines. Various silicon carbide (SiC) high temperature sensors, actuators, and electronics have been demonstrated at and above 500C. A compatible packaging system is essential for long-term testing and eventual applications of high temperature electronics and sensors. High temperature passive components are also necessary for high temperature electronic systems. This talk will discuss ceramic packaging systems developed for high electronics and related testing results of SiC circuits at 500C and silicon-on-insulator (SOI) integrated circuits at temperatures beyond commercial limit facilitated by high temperature packaging technologies. Dielectric materials for high temperature multilayers capacitors will also be discussed.

dielectric performance↗

NASA NTRS2003

Single-event upset in evolving commercial silicon-on-insulator microprocessor technologies

Single-event upset effects from heavy ions are measured for Motorola and IBM silicon-on-insulator (SOI) microprocessors with different feature sizes and core voltages. Multiple-bit upsets (MBU) in registers and were measured and compared with single-bit upsets. Also, the scaling of the cross section with reduction of feature size for SOI microprocessors was discussed.

Yoder, G. I.↗

NASA NTRS2024

The Plasma Proton Environment within Saturn’s F-G Ring Gap as Observed by the Cassini Plasma Spectrometer Ion Mass Spectrometer during Saturn Orbit Insertion

We report on the detection of protons and the potential detection of H 2 + between Saturn's F and G rings based on Cassini Plasma Spectrometer (CAPS) Ion Mass Spectrometer (IMS) time-of-flight (TOF) composition measurements acquired during Saturn Orbit Insertion (SOI) outbound pass. The range in dipole L shell is 2.3 < L < 2.8. Initial results based on TOF data were presented in E. C. Sittler et al., 2017. Here we present the latest results of our analysis. During the SOI outbound pass between the F and G rings the CAPS IMS was in a mode of reduced post-acceleration voltage at -6 kV instead of the usual -14.6 kV. This reduced voltage still allows the analysis of protons since 6 keV protons are minimally scattered by the instrument’s ultrathin carbon foils when compared to heavier ions O + and O 2 + , scattering. Background noise from penetrating radiation and ghost peaks produced by foil-scattered O + ions within the instrument were considered in our analysis. The analysis allowed determination of the proton density, temperature and flow velocity, accounting for spacecraft potential by assuming a convected Maxwellian for the proton velocity distribution function. We find average proton density n P = 3.2 ± 1.1 #/cm 3 , proton temperature T P = 1.74 ± 0.12 eV, proton rotational flow speed V P = 24 ± 1.5 km/s and spacecraft potential  SC = -0.8 ±1.5 V. These results are compared with previous theoretical estimates of H + and H 2 + ions within Saturn’s inner magnetosphere.

E C Sittler↗