SEARCH · Search NASA
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
Explore the source record for details and available documents.
Explore the source record for details and available documents.
Explore the source record for details and available documents.
The application of exterior insulation in both new construction and retrofits is a common practice to enhance the energy efficiency of buildings. In addition to increased thermal performance, the rigid insulation can serve to keep the sheathing board warm and serve as a water-resistive barrier to keep moisture-related problems due to condensation and wind-driven rain. Polyisocyanurate (PIR) rigid boards have a higher thermal resistance in comparison to other commonly used exterior insulation boards. However, because of its perceived lower permeance, its use as exterior insulation is not very common. In this study, the hygrothermal property of PIR boards with different facer types and thicknesses is characterized. The material data obtained through experimental test and extrapolation is used in a long term hygrothermal performance assessment of a wood frame wall with PIR boards as exterior insulation. Results show that PIR with no facer has the smallest accumulated moisture on the sheathing board in comparison to other insulation boards. Walls with a bigger thickness of exterior insulation perform better when no vapor barrier is used. The PIR exterior insulation supports the moisture control strategy well in colder climates in perfect wall scenarios, where there is no air leakage and moisture intrusion. In cases where there is trapped moisture, the sheathing board has a higher moisture content with PIR boards with both aluminum or fiberglass type facers. An innovative facer material development for PIR boards can help efforts targeting improved energy-efficient and durable wall systems.
Sensor assemblies are provided for use in modeling water systems. These sensor assemblies can be used as sensor fish. These assemblies can include a circuit board supporting processing circuitry components on either or both opposing component support surfaces of the circuit board and a housing above the circuit board and the components, with the housing being circular about the circuit board in at least one cross section, and wherein the supporting surfaces of the circuit board are substantially parallel with the plane of the housing in the one cross section. Methods for emulating interaction of entities within water systems are provided. The methods can include introducing a sensor assembly into a water system. The sensor assembly can include: a circuit board supporting processing circuitry components on either or both of opposing component support surfaces of the circuit board; a housing about the circuit board and the components, the housing being circular about the circuit board in at least one cross section; and wherein the support surfaces of the circuit board are substantially parallel with the plane of the housing in the one cross section.
The first board section comprises a switching module with heat-generating semiconductor switches associated with a first operational temperature range. The first board section has a first conductive layer of a first thickness. The second board section comprises a plurality of capacitors mounted on a second circuit board. The second board section has conductive traces for interconnecting the capacitors as a network. The capacitors are associated with a second operational temperature range that is lower than the first operational temperature range. A thermal isolation intermediary forms a barrier between, or adjoining, the first board section and the second board section, where the first board section and the second board section are spaced part from each other by the thermal isolation intermediary.
We describe an electronics system to operate SIPMs in the laboratory. The system is comprised of a single channel amplifier board (SIPM Amp) and a 4-channel control board to which up to 4 SIPM Amp boards can be connected. The control board supplies a common low voltage power for the amplifiers. All channels feature individually regulated bias and Peltier power voltages, along withPt10K RTD readout. A graphical user interface allows control of the bias voltages, amplifier voltage, Peltier voltages, and also provides for readback of leakage currents and other voltages. The GUI app has a feedback loop to measure the SIPM temperature (with the PT10K) and generate correction voltages to the Peltier to regulate the temperature. The temperatures, which can be achieved by Peltier cooling depend on the thermal design of the setup, the practical limit being about 50C below ambient. The SIPM Amp. board is a small (3x5cm) PCB that has a single SIPM readout channel. The SIPM scan be surface mounted on the pcb or connected to a 2-pin 0.100" socket. The area around the SIPM footprint is thermally isolated by perforations in the PCB. The RTD is located inside the thermal break. Onboard is BV and LV filtering. The 10X amplifier is based on MiniCircuits' GALI-S66+ integrated circuit, tweaked for a 6V power. The amplifier was selected for a combination of high bandwidth, low noise, and low power. An accoupled amplifier output is connected to an SMA connector. For best operation of this inverting amplifier the output signal should be in the range of 0 to -1V.The Amplifier board is connected to the Control board with a 10-conductor 0.025" pitch ribbon cable, carrying all the services. Peltier power for currents more than 1A should use a separate 2-contact connector.
This paper discusses power electronics developed under the ARPA-E GAMOW program to support nuclear fusion power production. The goal of this project was to develop and assess the potential for wide-bandgap (WBG) semiconductor devices in power electronics to enable high-efficiency and high-voltage solid-state systems for fusion plasma generation, heating, and control. The power electronics use an architecture in which multiple high-power boards can be combined to produce megawatt-level power, where using multiple boards provides high reliability. Two main areas of power electronics boards are developed in this project for fusion plasma heating and control applications: (1) pulse generation and control and (2) radiofrequency generation. The first area is for boards capable of driving high-voltage millisecond pulses at high duty cycles. The envisioned application of these pulses is in plasma control of magnetohydrodynamic instabilities, plasma position, and edge-localized modes. Pulse-width modulation allows for the implementation of a wide variety of linear and nonlinear control systems. The boards developed for this project could actuate control coils based on digital input signals and can be parallelized to provide megawatts of output power. The design of the pulse generator is a low-side load switch. A load switch was designed and constructed that utilized 2-kV-rated field-effect transistor (FET)-based cascodes developed by Qorvo under this project to perform initial testing of these cascodes. The second area is being implemented using class E amplifiers with WBG devices and a reactance steering network to handle inductive or capacitive plasma loads. Applications include ion cyclotron resonance heating (ICRH) and high-harmonic fast-wave (HHFW) heating. A class E reactance steering network is demonstrated in modeling and experiment with a resistive-inductive load that models an inductively-coupled plasma. Power combining of boards with class E reactance steering networks is also simulated and demonstrated experimentally, to enable scaling up to high power. Modeling of high-power-density cooling and remaining useful life is conducted to enable reliable, effectively cooled high-power electronics for fusion applications.
The Ultra-Fast X-ray Imager (UXI) program is an ongoing effort at Sandia National Laboratories to create high speed, multi-frame, time-gated Read Out Integrated Circuits (ROICs), and a corresponding suite of photodetectors to image a wide variety of High Energy Density (HED) physics experiments on both Sandia’s Z-Machine and LLNL’s National Ignition Facility (NIF). Several cameras have been designed over the length of the program; one of the most recent is the Icarus, which is an improvement on past imagers (Furi and Hippogriff). A second sensor that can be connected is the Daedalus sensor. The Icarus is a 1024 × 512-pixel array with either 25 μm or 8 µm spatial resolution containing four frames of storage per pixel and has improved timing generation and distribution components while achieved 2 ns time gating. The Daedalus sensor is also a 1024 x 512-pixel array with 25 µm special resolution containing three frames of storage per pixel and has an increased set of features for a wider variety of applications from interlacing of rows in each frame to configurability of all shutters. See Section 14 for details regarding the Icarus implementation of the firmware and Section 15 for details regarding the Daedalus implementation. Due to the unique test environments UXI sensors are targeted for, full custom hardware was required to physically mount an Icarus or Daedalus sensor, manage its various functions, and read out pixel data for transfer to a host computer. Beyond experimental functionality, the hardware also needed to accommodate sensor characterization requirements. Lawrence Livermore National Laboratory’s ‘Version 4.0 Board’ was the result of these efforts. It mounts all the components required to fully utilize the Icarus and Daedalus sensors including analog to digital converters to convert pixel data and various system voltages to digital form for readout and analysis, DAC channels for remote configuration of critical bias voltages, static random-access memories to buffer pixel data, RS422 and Gigabit Ethernet communications for remote access, and an FPGA to tie these components together. This document describes the FPGA electrical interfaces in detail to allow the reader a greater understanding of the device, and to facilitate implementation of custom software to control and manage it. The Version 4.0 Board is a continuation of the Nano-second Gated CMOS hardware design that retains much of the functionality of the Version 1.0 Board while adding features including a DAC instead of digital potentiometers, as well as sensors for pressure and radiation. The Version 4.0 board is intended for applications requiring tight form-factor enclosures. It is composed of two stacking boards; one holds the FPGA and regulators to power the various components of the board while the other contains the mating connector to the sensor, image-readoff ADCs, the DAC, and other components.
Embodiments of the present invention include systems for launching primary or secondary payloads or actuating other launch vehicle or payload or instrumentation devices. The system includes an adapter assembly and at least one sequencer mounted to the adapter assembly. The sequencer includes: controller boards, each of the controller boards having a controller for controlling deployment of the payloads and data files; output ports coupled to the controller boards and configured to transmit signals from the controller boards to dispensers therethrough, deployment mechanisms containing the payloads, the adapter assembly having channels for accommodating the dispensers; and a detector coupled to the controller boards and adapted to detect an external signal and, in response to the external signal, to send an initiation signal to the controller boards. The system also includes at least one power supply coupled to the sequencer and adapted to provide an electrical power to the sequencer.
Printed circuit Boards (PCBs) are becoming increasingly vulnerable to malicious design alteration, also known as Trojan attacks, due to a distributed business model that often involves various untrusted parties. Such attacks can be mounted at various stages in the PCB life cycle. The relative ease of alteration of PCB hardware even after fabrication (due to physical access to surface-mounted critical components and traces) makes them attractive for an adversary to manipulate their functional/physical behavior for malicious intent. There is a growing need to explore viable Trojan attacks in a PCB, analyze their functional and physical characteristics (e.g., impact on power or delay), and study the effectiveness of countermeasures against these attacks. While simulation-based approaches for PCB Trojan insertion are effective at creating a large population of possible Trojans, they fail to provide functional feasibility analysis with a realistic workload for a trigger circuit. Also, they cannot estimate a Trojan’s side-channel footprint due to the unavailability of physical models of diverse PCB components. To address these deficiencies, in this paper, we present PRISTINE, a PCB-level emulation system for any integrity or physical tampering issues, specifically, hardware Trojan insertion. The need for building such an emulation platform to resolve PCB trust issues in the supply chain is also surveyed and discussed. Both custom Hardware Hacking (HaHa) boards and multiple commercial PCBs are then used to test the ability of the proposed system to emulate various hardware Trojans specially designed to exploit board-specific hardware characteristics. Experimental results on emulated board-level Trojans show that a wide range of Trojans can be successfully activated, thus enabling the expected payload effects on both types of boards to be studied and quantified. The resulting data are further analyzed to create PCB-level Trojan benchmarks. In particular, a comparative evaluation of the experimental results is used to propose a risk level metric that quantifies the probability of detection and degree of payload impact of each Trojan on a given commercial PCB.
The board game industry revenue has seen rapid growth from 6.2 billion USD to a projected 8.6 billion USD in revenue from 2018 to 2024 indicating an increased demand for this style of product. Inflation, shipping and the cost of raw materials have increased the cost for producing board games. This increased the barrier of entry and reduces profit margins. Many people lose the chance to experience much of the catalogue of modern hobby board games because of this. There is a need for a digital and low-cost solution for buyers to fulfill demand and create a steady supply while maintaining the characteristics that make board games attractive to consumers. Lowering the barrier of entry will allow for more consumers to enter the market and provide a catalyst for growth in the board game community.
An electrical connector carries large amounts of electrical current between two circuit boards with low resistance and low self-inductance by means of an interdigitated anode and cathode, thereby providing low dynamic voltage loss. The connector also may include, near where power will be consumed, an interposer board with on-board capacitance to provide even lower dynamic voltage loss. The connector has application to delivering low-voltage, high-current power from a power supply on a first board to electronics on a second board: the low resistance provides low voltage drop for a load current that is constant, while the low inductance and the capacitors provide low voltage fluctuation for a load current that changes. These issues are of great importance, for example, in designing high-performance computers.
The U.S. Nuclear Waste Technical Review Board (Board) has been interested for many years in the Department of Energy (DOE) activities related to transporting spent nuclear fuel (SNF) and high-level radioactive waste (HLW). The Board has conducted several public meetings and issued associated reports on this topic. In September 2019, the Board issued a report entitled Preparing for Nuclear Waste Transportation-Technical Issues that Need to Be Addressed in Preparing for a Nationwide Effort to Transport Spent Nuclear Fuel and High-Level Radioactive Waste [1] that focuses on the issues DOE will need to address to plan and implement an integrated transportation program. In its report, the Board describes 30 broad technical issues that DOE needs to address and offers three sets of findings and recommendations to DOE. (authors)
Methods for emulating interaction of entities within water systems are provided. The methods can include introducing a sensor assembly into a water system. The sensor assembly can include: a circuit board supporting processing circuitry components on either or both of opposing component support surfaces of the circuit board; a housing about the circuit board and the components, the housing being circular about the circuit board in at least one cross section; and wherein the support surfaces of the circuit board are substantially parallel with the plane of the housing in the one cross section.
In conventional multi-cylinder drying of paper and board, both conductive drying from steam-heated dryer cylinders and convective drying by flowing air over the paper surface in the pockets are used. Conductive drying from steam-heated drying cylinders is a critical component in providing the necessary thermal energy to paper and board as they dry. Steam temperature and internal and external resistances at the contacting surface are critical process parameters influencing the conductive drying process. An experimental setup was developed to study the alternating conductive and convective drying of paper and board. Paper sheet moisture, temperature, and temperature distribution within the heated platen and the instantaneous heat flux as the sheet was being dried were measured. The instantaneous heat flux, contact heat transfer coefficient, and drying rates were determined as drying proceeds. Experimental results, as well as comparisons to literature and commercial data, are presented. The conductive heat transfer coefficients determined were compared to traditional correlations normally used in the modeling of paper drying. Similarly, the convective heat and mass transfer coefficients are also determined and compared to literature data. In addition to the evaluation of alternating conductive and convective drying characteristics of paper and board, the potential inclusion of auxiliary energy components will also be included. Experimental results from the conduction and convection drying system are presented. Furthermore, this data will be useful in process development, intensification of manufacturing processes, and modeling and simulation of paper drying processes.
A self-synchronizing underwater acoustic network, designed for remote monitoring of mooring loads in Wave Energy Converters (WEC), has been developed and tested. This network uses Time Division Multiple Access and operates self-contained with the ability for users to remotely transmit commands to the network as needed. Each node is a self-contained unit, consisting of a protocol adaptor board, an underwater acoustic modem and a battery pack. A node can be connected to a load cell, to a topside user or to the WEC. Every node is swapable. The protocol adaptor board, named Protocol Adaptor for Digital LOad Cell (PADLOC) supports a variety of digital load cell message formats (CAN, MODBUS, custom ASCII) and underwater acoustic modem serial formats. PADLOC enables topside users to connect to separate load cells through a user-specific command.
the Xilinx tools relay on a component on the board (FTDI chip) to have a small memory from a particular manufacturer (Digilent) to serve as a bridge to the FPGA. What the software we're requesting to release simply does is to run between the Xilinx tools (one of them is called Vivado but there are others) and our boards so that we don't need that memory on our boards. The protocol the software uses to communicate with the Xilinx tools is called XVC (Xilinx Virtual Cable). This server code runs on the computer that is physically connected to the FPGA board, but the Xilinx tools that communicate with it can run either on that computer or some other computer connected to it over the network, this is where the network component comes into play.