SEARCH · Search NASA
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
This letter reports the performance of a novel single-stage W-band amplifier fabricated utilizing flip-chip bump-bonding. We have bump-bonded a high-speed, low-noise InP high electron mobility transistor (HEMT) device onto a separately fabricated passive circuit having a GaAs substrate.
The popularity of emerging miniaturized Chip Scale Packages (CSPs) is rapidly growing because of their benefits and smaller size.
This paper reports a preliminary study result of an on-board spaceborne SAR processor. It consists of a processing requirement analysis, functional specifications, and implementation with system-on-chip technology. Finally, a minimum version of this on-board processor designed for performance evaluation and for partial demonstration is illustrated.
Due to low ESR and safe failure mode, new technology chip polymer tantalum capacitors (CPTC) have gained popularity in the electronics design community, first in commercial applications, and now in hi-rel and space systems. The major drawbacks of these parts are high leakage currents, degradation under environmental stresses, and a relatively narrow temperature range of operating and storage conditions. Several studies have shown that a certain amount of moisture in polymer cathodes is necessary for a normal operation of the parts. This might limit applications of CPTCs in space systems and requires analysis of long-term exposure to deep vacuum conditions on their performance and reliability. High leakage currents and limited maximum operational temperature complicate accelerated testing that is necessary to assess long-term reliability and require new screening and qualification procedures for quality assurance. A better understanding of behavior of CPTCs as compared to traditional, MnO2, capacitors is necessary to develop adequate approaches for QA system for space applications. A specific of CPTCs is that different materials and processes might be used for low-voltage (10 V and less) and high-voltage (above 10 V) capacitors, so performance and degradation processes in these groups require separate analysis. In this work, that is a part of the NASA Electronic Parts and Packaging (NEPP) program, degradation of AC and DC characteristics under environmental stresses at different temperatures and voltages have been studied in nine lots of commercial and automotive grade capacitors rated to 10 V. Results of analysis of leakage currents, high temperature storage (HTS) up to 5000 hrs in vacuum and air at different temperatures, and Highly Accelerated Life Testing (HALT) in the range from 85 C to 145 C are presented. Temperature and voltage acceleration factors were calculated based on approximation of distributions of degradation rates with a general log-linear Weibull model. Mechanisms of degradation and failures, and requirements for screening and qualification testing are discussed.
One of the main health risks in human space exploration is central nervous system (CNS) damage by ionizing radiation due to exposure to the galactic cosmic rays (GCRs). In animal models, irradiation with simulated GCRs or their components has been shown to cause neuronal damage and neuroinflammation associated with cognitive and behavioral dysfunction. In general, the extent of CNS damage is partially regulated by the blood-brain barrier (BBB), which enables immune cells to enter the CNS. The main cellular regulators of BBB permeability are astrocytes, which also modulate neuronal death, immune responses and oxidative stress, and thus could serve as a robust CNS-specific target for countermeasure development. However, studies on BBB permeability and astrocyte functions in regulating CNS responses to ionizing radiation have been limited, especially in human tissue/organ analogs. Therefore, we established a high-throughput 3D organ-on-a-chip system to study human CNS and BBB impairments in response to ionizing radiation, based on commercially available OrganoPlates (Mimetas, Inc.) seeded with primary or induced pluripotent stem cell-derived human cells. We investigated both immediate and delayed CNS responses to major GCR components: 0.15-0.5 Gy 250MeV/n 4-He, and 0.3-0.8 Gy 600 MeV/n 56-Fe; as well as to 0.5-1 Gy X-rays. We observed ionizing radiation-mediated increases in BBB permeability that was exacerbated by astrocyte presence and accompanied by morphological changes in endothelial cells and tight junctions, altered cytokine profile including TNFa upregulation, and increased oxidative stress. We also quantified irradiation-mediated changes in astrocyte activation and neuronal functions, revealing major astrocyte damage mediated by 600MeV/n 56-Fe particles. Thus, we demonstrate that deep space radiation may contribute to CNS damage by disrupting both astrocyte and endothelial cell components of the blood-brain barrier. Our next steps include mapping and validating the transcriptomic changes induced by simulated GCRs and their components in human CNS models. Ultimately, we aim to uncover potential novel targets for countermeasure developments to mitigate CNS damage in long duration spaceflight.
Different aspects of advanced surface mount package technology have been investigated for aerospace applications. Three key areas included the assembly reliability of conventional Surface Mount, Ball Grid Arrays (BGAs), and Chip Scale Packages.
On-chip p-FETs were developed to monitor the radiation dose of n-well CMOS ICs by monitoring the threshold voltage shifts due to radiation induced oxide and interface charge.
Availability of board solder joint reliability information is critical to the wider implementation of Chip Scale Packages (CSPs).
This paper reviews many factors that affect interconnect reliability of commercial-off-the-shelf (COSTS) chip scale package (CSP) assemblies.
In this paper, an ultra-fast smart vision system-on-a-chip design is proposed to provide effective solutions for real time machine vision applications by taking advantages of recent advances in integrated sensing/processing designs, electronic neural networks, advanced microprocessors and sub-micron VLSI technology.
Device is developed to control the force used in manually placing chips on substrates. It controls the compression load between 2 small members at loads as low as 25 grams by means of a force control gage that is preset by varying the spring deflection.
Fracture phenomena in plastics cutting - chip types, deformation of material, magnitude, and direction of cutting forces during cutting, and rheological effects on cutting mechanism
Fabrication technique for direct interconnection of uncased silicon integrated circuit chips
Encapsulation technique for multiple chip silicon switching transistors with silver-Teflon contacts
Breaking of semiconductor single crystal wafer into chips
Several cycles of photoetching, dopant deposition, and drive-in produce selectively-doped regions and semiconductor junctions within a single chip.
Combination of complementary MOS and complementary bipolar circuits on monolithic silicon chip
Mechanical design modifications, processing, and test data for high power, low saturation voltage, multi-chip silicon switching transistor