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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
NASA NTRS2013

An Approach for the Assessment of System Upset Resilience

This report describes an approach for the assessment of upset resilience that is applicable to systems in general, including safety-critical, real-time systems. For this work, resilience is defined as the ability to preserve and restore service availability and integrity under stated conditions of configuration, functional inputs and environmental conditions. To enable a quantitative approach, we define novel system service degradation metrics and propose a new mathematical definition of resilience. These behavioral-level metrics are based on the fundamental service classification criteria of correctness, detectability, symmetry and persistence. This approach consists of a Monte-Carlo-based stimulus injection experiment, on a physical implementation or an error-propagation model of a system, to generate a system response set that can be characterized in terms of dimensional error metrics and integrated to form an overall measure of resilience. We expect this approach to be helpful in gaining insight into the error containment and repair capabilities of systems for a wide range of conditions.

Torres-Pomales, Wilfredo↗
NASA NTRS2016

Survey of Quantitative Research Metrics to Assess Pilot Performance in Upset Recovery

Accidents attributable to in-flight loss of control are the primary cause for fatal commercial jet accidents worldwide. The National Aeronautics and Space Administration (NASA) conducted a literature review to determine and identify the quantitative standards for assessing upset recovery performance. This review contains current recovery procedures for both military and commercial aviation and includes the metrics researchers use to assess aircraft recovery performance. Metrics include time to first input, recognition time and recovery time and whether that input was correct or incorrect. Other metrics included are: the state of the autopilot and autothrottle, control wheel/sidestick movement resulting in pitch and roll, and inputs to the throttle and rudder. In addition, airplane state measures, such as roll reversals, altitude loss/gain, maximum vertical speed, maximum/minimum air speed, maximum bank angle and maximum g loading are reviewed as well.

Le Vie, Lisa R.↗
NASA NTRS2017

NEPP Update of Independent Single Event Upset Field Programmable Gate Array Testing

This presentation provides a NASA Electronic Parts and Packaging (NEPP) Program update of independent Single Event Upset (SEU) Field Programmable Gate Array (FPGA) testing including FPGA test guidelines, Microsemi RTG4 heavy-ion results, Xilinx Kintex-UltraScale heavy-ion results, Xilinx UltraScale+ single event effect (SEE) test plans, development of a new methodology for characterizing SEU system response, and NEPP involvement with FPGA security and trust.

Field Programmable Gate Array (FPGA); Triple Modul↗
NASA NTRS2004

Frequency dependence of single-event upset in advanced commercial PowerPC microprocessors

Single-event upset (SEU) from heavy ions is measured for advanced commercial microprocessors in a dynamic mode with clock frequencies up to 1 GHz. Frequency and core voltage dependence of SEUs in registers and D-Cache are discussed. The results of our studies suggest the SEU in registers and D-Cache tend to increase with frequency. This might have important implications for the overall SEU trend as technology moves toward higher frequencies.

Farmanesh, F. F.↗
NASA NTRS1997

Single-Event Upset in Flash Memories

This paper discusses single-event upset effets in flash memories, using heavy ions at the Texas A&M cyclotron. Initial results are presented for one manufacturer that compare uspet in the individual memory elemts with the more complex funtion failure modes that occur in the internal state machine and its control registers. This device is designed to function with either 5-V or 3.3-V power supply levels for read operations, but requires an additional 5 or 12-V power supply for write and erase operations.

Flash↗
NASA NTRS2000

Angular dependence of DRAM upset susceptibility

Heavy ion irradiations of two types of commercial DRAMs reveal unexpected angular responses. One device's cross section varied by two orders of magnitude with azimuthal angle. Accurate prediction of space rates requires accommodating this effect.

DRAM angle SEU multiple bit upset DRAM upsets↗
NASA NTRS2014

Independent Single Event Upset Testing of the Xilinx V5QV

In this presentation, we provide a brief glimpse at preliminary single event test results taken from two years of testing of the Xilinx V5QV Field Programmable Gate Array (FPGA). This presentation includes an overview of test philosophy and implementation.

Single Event Upset Testing↗
NASA NTRS2015

Using Classical Reliability Models and Single Event Upset (SEU) Data to Determine Optimum Implementation Schemes for Triple Modular Redundancy (TMR) in SRAM-Based Field Programmable Gate Array (FPGA) Devices

Space applications are complex systems that require intricate trade analyses for optimum implementations. We focus on a subset of the trade process, using classical reliability theory and SEU data, to illustrate appropriate TMR scheme selection.

Field Programmable Gate Array (FPGA)↗
NASA NTRS2001

Single-event upset in the PowerPC750 microprocessor

In this paper we report results of single-event tests of the PowerPC750 from Motorola and IBM, which are identical designs which are manufactured with advanced processes that uses a minimum feature size of 0.29 and 0.28 mu m, respectively.

single↗
NASA NTRS2000

In-flight observations of multiple-bit upset in DRAMs

In-flight data is examined showing a very high incidence of multiple-bit errors in a solid-state recorder that incorporates error detection and correction. The high MBU rate is shown to be a consequence of the physical selection of memory cell locations in the recorder architecture.

single↗