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At least 163 records · Page 9

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NASA NTRS2010

180-GHz I-Q Second Harmonic Resistive Mixer MMIC

An indium phosphide MMIC (monolithic microwave integrated circuit) mixer was developed, processed, and tested in the NGC 35-nm-gate-length HEMT (high electron mobility transistor) process. This innovation is very compact in size and operates with very low LO power. Because it is a resistive mixer, this innovation does not require DC power. This is an enabling technology for the miniature receiver modules for the GeoSTAR instrument, which is the only viable option for the NRC decadal study mission PATH.

Kangaslahti, Pekka P.↗

NASA NTRS1976

Radiation design criteria handbook

Radiation design criteria for electronic parts applications in space environments are provided. The data were compiled from the Mariner/Jupiter Saturn 1977 electronic parts radiation test program. Radiation sensitive device types were exposed to radiation environments compatible with the MJS'77 requirements under suitable bias conditions. A total of 189 integrated circuits, transistors, and other semiconductor device types were tested.

Stanley, A. G.↗

NASA NTRS2000

Modernization and Activation of the NASA Ames 11- by 11-Foot Transonic Wind Tunnel

The Unitary Plan Wind Tunnel (UPWT) was modernized to improve performance, capability, productivity, and reliability. Automation systems were installed in all three UPWT tunnel legs and the Auxiliaries facility. Major improvements were made to the four control rooms, model support systems, main drive motors, and main drive speed control. Pressure vessel repairs and refurbishment to the electrical distribution system were also completed. Significant changes were made to improve test section flow quality in the 11-by 11-Foot Transonic leg. After the completion of the construction phase of the project, acceptance and checkout testing was performed to demonstrate the capabilities of the modernized facility. A pneumatic test of the tunnel circuit was performed to verify the structural integrity of the pressure vessel before wind-on operations. Test section turbulence, flow angularity, and acoustic parameters were measured throughout the tunnel envelope to determine the effects of the tunnel flow quality improvements. The new control system processes were thoroughly checked during wind-off and wind-on operations. Manual subsystem modes and automated supervisory modes of tunnel operation were validated. The aerodynamic and structural performance of both the new composite compressor rotor blades and the old aluminum rotor blades was measured. The entire subsonic and supersonic envelope of the 11-by 11-Foot Transonic leg was defined up to the maximum total pressure.

Kmak, Frank J.↗

NASA NTRS2013

RESOLVE Project

The RESOLVE project is a lunar prospecting mission whose primary goal is to characterize water and other volatiles in lunar regolith. The Lunar Advanced Volatiles Analysis (LAVA) subsystem is comprised of a fluid subsystem that transports flow to the gas chromatograph - mass spectrometer (GC-MS) instruments that characterize volatiles and the Water Droplet Demonstration (WDD) that will capture and display water condensation in the gas stream. The LAVA Engineering Test Unit (ETU) is undergoing risk reduction testing this summer and fall within a vacuum chamber to understand and characterize component and integrated system performance. Testing of line heaters, printed circuit heaters, pressure transducers, temperature sensors, regulators, and valves in atmospheric and vacuum environments was done. Test procedures were developed to guide experimental tests and test reports to analyze and draw conclusions from the data. In addition, knowledge and experience was gained with preparing a vacuum chamber with fluid and electrical connections. Further testing will include integrated testing of the fluid subsystem with the gas supply system, near-infrared spectrometer, WDD, Sample Delivery System, and GC-MS in the vacuum chamber. This testing will provide hands-on exposure to a flight forward spaceflight subsystem, the processes associated with testing equipment in a vacuum chamber, and experience working in a laboratory setting. Examples of specific analysis conducted include: pneumatic analysis to calculate the WDD's efficiency at extracting water vapor from the gas stream to form condensation; thermal analysis of the conduction and radiation along a line connecting two thermal masses; and proportional-integral-derivative (PID) heater control analysis. Since LAVA is a scientific subsystem, the near-infrared spectrometer and GC-MS instruments will be tested during the ETU testing phase.

Parker, Ray↗

NASA NTRS2015

RESOLVE (Regolith & Environmental Science Oxygen & Lunar Volatile Extraction) Project

The RESOLVE Project is a lunar prospecting mission whose primary goal is to characterize water and other volatiles in lunar regolith. The Lunar Advanced Volatiles Analysis (LAVA) subsystem is comprised of a fluid subsystem that transports flow to the gas chromatograph - mass spectrometer (GC-MS) instruments that characterize volatiles and the Water Droplet Demonstration (WDD) that will capture and display water condensation in the gas stream. The LAVA Engineering Test Unit (ETU) is undergoing risk reduction testing this summer and fall within a vacuum chamber to understand and characterize component and integrated system performance. Testing of line heaters, printed circuit heaters, pressure transducers, temperature sensors, regulators, and valves in atmospheric and vacuum environments was done. Test procedures were developed to guide experimental tests and test reports to analyze and draw conclusions from the data. In addition, knowledge and experience was gained with preparing a vacuum chamber with fluid and electrical connections. Further testing will include integrated testing of the fluid subsystem with the gas supply system, near-infrared spectrometer for the Surge Tank (NIRST), WDD, Sample Delivery System, and GC-MS in the vacuum chamber. Since LAVA is a scientific subsystem, the near infrared spectrometer and GC-MS instruments will be tested during the ETU testing phase.

LAVA↗

NASA NTRS1983

Solid State Circuits for Cryogenic Operation

Tests confirm operation of five commercial semiconductor devices at cryogenic temperatures. The five devices - one tunnel diode, one field-effect transistor, and three CMOS integrated circuits - all perform well in circuits immersed in liquid-helium bath. For some tests, bath temperature was reduced to 1,25K by pumping.

Petrac, D.↗

NASA NTRSDate not supplied

Electrical and Dielectric Characterizations of HTCC Electronic Packages for High Temperature Harsh Environment Applications

A prototype high temperature co-fired ceramic (HTCC) alumina packaging system composed of a 32-I/Os package and a compatible circuit board was previously developed and demonstrated for long term operation in 500 °C environments. The electrical / dielectric parasitic parameters of that chip level package were characterized and reported. This co-fired packaging system with platinum (Pt) conductor has successfully facilitated tests of silicon carbide (SiC) analog and digital integrated circuits (ICs) developed at NASA GRC at 500°C for up to 10,000 hours in ambient oven environment and 60 earth days in Venus surface environment with simulated temperature, pressure, and chemical constituents. Based on these previous results, this paper introduces new designs of Pt-HTCC packages with 16, 24, and 44 I/Os for packaging a new generation SiC ICs with 8, 24, 56, 62, and 72 I/Os to be tested in high temperature harsh environments. The package with 44 I/Os is specifically designed for the new SiC ICs with 56, 62, and 72-I/Os and electrical connection needs, the power pads of this package are consolidated, and an array of I/O pads distributed on separated vertical levels (inside the package) is used to control the overall package dimensions and mitigate the parasitic effects at high temperatures. This paper will present the detailed design of these chip-level packages and results of electrical and dielectric characterization of these newly fabricated chip-level Pt-HTCC packages.

High temperature↗

NASA NTRSDate not supplied

Electrical and Dielectric Characterizations of HTCC Electronic Packages for High Temperature Harsh Environment Applications

High temperature↗

NASA NTRS1975

Hardening of MJS77 spacecraft against the Jupiter radiation belts

Results of the device characterization program to identify components of the Mariner Jupiter/Saturn spacecraft in need of radiation hardening to meet a total dose requirement of 5 trillion e/sq cm are presented. The parts to be tested, including bipolar transistors, JFETs, SCRs, CMOS devices, linear integrated circuits, Zener diodes and other radiation-sensitive parts, were identified by a worst case circuit analysis of the 20 major subsystems. The test samples were exposed to several levels of irradiation from a Dynamitron electron accelerator capable of producing a steady stream of electrons at energies up to 2.5 eV. The electrical parameters of the devices were measured immediately following irradiation to prevent annealing. CMOS devices and linear devices showed the most severe degradation in a moderate radiation environment, and significant degradation was produced at low current in bipolar transistors. Three methods used for screening a number of devices determined by circuit and shielding analyses to be unacceptable radiation-sensitive are described: diffusion and metallization lot screening; wafer lot screening; and irradiation-anneal screening.

W E Price↗

NASA NTRS2015

Complex Parts, Complex Data: Why You Need to Understand What Radiation Single Event Testing Data Does and Doesn't Show and the Implications Thereof

Electronic parts (integrated circuits) have grown in complexity such that determining all failure modes and risks from single particle event testing is impossible. In this presentation, the authors will present why this is so and provide some realism on what this means. Its all about understanding actual risks and not making assumptions.

NASA Electronic Parts and Packaging (NEPP) Program↗

NASA NTRS1998

Use of SX Series Devices and IEEE 1149.1 JTAG Circuitry

This report summarizes the use of SX series devices and their JTAG 1149.1 circuitry. 'JTAG' circuitry was originally designed to standardize testing of boards via a simple control port interface electrically without having to use devices such as a bed of nails tester. JTAG is also used for other functions such as executing built-in-test sequences, identifying devices, or, through custom instructions, other functions designed in by the chip designer. The JTAG circuitry is designed for test only; it has no functional use in the integrated circuit during normal operations. The JTAG circuitry and the mode of the device is controlled by a circuit block known as the 'TAP controller,' which is a sixteen-state state machine along with various registers. The controller is normally in an operational state known as TEST-LOGIC-RESET. In this state, the device is held in a fully functional, operating mode. However, a Single Event Upset (SEU) may remove the TAP controller from this state, causing a loss of control of the integrated circuit, unless certain precautions are taken, such as grounding the optional JTAG TRST signal.

Katz, Richard B.↗

NASA NTRS1998

Use of SX Series Devices and IEEE 1149.1 JTAG Circuitry

This report summarizes the use of SX series devices and their JTAG 1149.1 circuitry. 'JTAG' circuitry was originally designed to standardize testing of boards via a simple control port interface electrically without having to use devices such as a bed of nails tester. JTAG is also used for other functions such as executing built-in-test sequences, identifying devices, or, through custom instructions, other functions designed in by the chip designer. The JTAG circuitry is designed for test only; it has no functional use in the integrated circuit during normal operations. The JTAG circuitry and the mode of the device is controlled by a circuit block known as the 'TAP controller,' which is a sixteen-state state machine along with various registers. The controller is normally in an operational state known as TEST-LOGIC-RESET. In this state, the device is held in a fully functional, operational mode. However, a Single Event Upset (SEU) may remove the TAP controller from this state, causing a loss of control of the integrated circuit, unless certain precautions are taken, such as grounding the optional JTAG TRST signal.

Katz, Richard B.↗

NASA NTRS1994

JTEC Panel report on microelectromechanical systems in Japan

This report summarizes recent activities in the development of microelectromechanical systems (MEMS) in Japan. For the purposes of this study, 'MEMS' means batch-fabricated miniature devices that convert physical parameters to or from electrical signals and that depend on mechanical structures or parameters in important ways for their operation. The report covers advanced materials and process technology; sensors and sensing microstructures; microactuators and actuation mechanisms; sensor-circuit integration and system partitioning; advanced packaging, microassembly, and testing technologies; and MEMS design techniques, applications, and infrastructure. The panel found that Japanese industry is emphasizing approaches to MEMS that are similar to those taken by U.S. industry (i.e., approaches based on silicon integrated-circuit technology); these efforts are comparable in their level of development to those in the United States. However, the ten-year, $250 million, MITI-sponsored program in micromachines emphasizes the miniaturization of more traditional (nonlithographic) machining processes, an area in which there is no comparable U.S. effort. Packaging technology and applications for batch-fabricated MEMS devices is considered a major challenge in both countries. The panel concluded that these and other issues will require global leadership and international cooperation to realize the benefits of MEMS in a timely way.

Wise, Kensall D.↗

NASA NTRS1975

Failure analysis of electronic parts: Laboratory methods

Failure analysis test methods are presented for use in analyzing candidate electronic parts and in improving future design reliability. Each test is classified as nondestructive, semidestructive, or destructive. The effects upon applicable part types (i.e. integrated circuit, transitor) are discussed. Methodology is given for performing the following: immersion tests, radio graphic tests, dewpoint tests, gas ambient analysis, cross sectioning, and ultraviolet examination.

Anstead, R. J.↗

NASA NTRS2006

Single Event Effects Test Results for Advanced Field Programmable Gate Arrays

Reconfigurable Field Programmable Gate Arrays (FPGAs) from Altera and Actel and an FPGA-based quick-turnApplication Specific Integrated Circuit (ASIC) from Altera were subjected to single-event testing using heavy ions. Both Altera devices (Stratix II and HardCopy II) exhibited a low latchup threshold (below an LET of 3 MeV-cm2/mg) and thus are not recommended for applications in the space radiation environment. The flash-based Actel ProASIC Plus device did not exhibit latchup to an effective LET of 75 MeV-cm2/mg at room temperature. In addition, these tests did not show flash cell charge loss (upset) or retention damage. Upset characterization of the design-level flip-flops yielded an LET threshold below 10 MeV-cm2/mg and a high LET cross section of about lxlO-6 cm2/bit for storing ones and about lxl0-7 cm2/bit for storing zeros . Thus, the ProASIC device may be suitable for critical flight applications with appropriate triple modular redundancy mitigation techniques.

Field Programmable Gate Arrays↗

NASA NTRS1968

Small, low power analog-to-digital converter

A small, low-power, high-speed, 8-bit analog-to-digital converter using silicon chip integrated circuits is suitable for use in airborne test data systems. The successive approximation method of analog-to-digital conversion is used to generate the digital output.

Dunn, R. D.↗

NASA NTRS1991

Analog VLSI neural network integrated circuits

Two analog very large scale integration (VLSI) vector matrix multiplier integrated circuit chips were designed, fabricated, and partially tested. They can perform both vector-matrix and matrix-matrix multiplication operations at high speeds. The 32 by 32 vector-matrix multiplier chip and the 128 by 64 vector-matrix multiplier chip were designed to perform 300 million and 3 billion multiplications per second, respectively. An additional circuit that has been developed is a continuous-time adaptive learning circuit. The performance achieved thus far for this circuit is an adaptivity of 28 dB at 300 KHz and 11 dB at 15 MHz. This circuit has demonstrated greater than two orders of magnitude higher frequency of operation than any previous adaptive learning circuit.

Kub, F. J.↗

NASA NTRS2018

Yearlong 500 °C Operational Demonstration of Up-Scaled 4H-SiC JFET Integrated Circuits

This work describes recent progress in the design, processing, upscaling, and testing of 500°C durable two-level interconnect 4H-SiC JFET IC technology undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for 1 year (8760 hours) at 500°C in air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500°C-durable circuit complexity from the 24 transistor ring oscillator ICs reported at HiTEC 2016.

Neudeck, Philip G.↗