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All sourcesNASA NTRSDOE OSTI
NASA NTRSDate not supplied

Risk-Based SMA and Modernizing Risk Classification at GSFC

In 2014, in response to a large volume of feedback from industry, the science community, and internal to Goddard Space Flight Center (GSFC), GSFC’s Safety and Mission Assurance (SMA) Directorate began a transition to a risk-based implementation of SMA, departing from its longstanding practice of being primarily driven by a mostly static set of Mission Assurance Requirements. The transition started out with a pilot project involving risk-based acceptance of bare-printed circuit boards that was enormously successful, continued through a complete organizational transformation in 2015, and culminated with the baselining of formal Risk-Based SMA policy in 2016. In this presentation we will describe the risk-based SMA concept, segue into how it shapes a modernization of risk classification that GSFC has rolled out, and provide results from the original pilot project for risk-based SMA, involving the printed circuit board assurance process.

Jesse Leitner↗
NASA NTRS2014

Modular Pulsed Plasma Electric Propulsion System for Cubesats

Current capabilities of CubeSats must be improved in order to perform more ambitious missions. Electric propulsion systems will play a key role due to their large specific impulse. Compared to other propulsion alternatives, their simplicity allows an easier miniaturization and manufacturing of autonomous modules into the nano and pico-satellite platform. Pulsed Plasma Thrusters (PPTs) appear as one of the most promising technologies for the near term. The utilization of solid and non-volatile propellants, their low power requirements and their proven reliability in the large scale make them great candidates for rapid implementation. The main challenges are the integration and miniaturization of all the electronic circuitry into a printed circuit board (PCB) that can satisfy the strict requirements that CubeSats present. NASA Ames and the George Washington University have demonstrated functionality and control of three discrete Micro-Cathode Arc Thrusters (CAT) using a bench top configuration that was compatible with the ARC PhoneSat Bus. This demonstration was successfully conducted in a vaccum chamber at the ARC Environmental Test Laboratory. A new effort will integrate a low power Plasma Processing Unit and two plasma thrusters onto a single printed circuit board that will utilize less than 13 U of Bus volume. The target design will be optimized for the accommodation into the PhoneSatEDISON Demonstration of SmallSatellite Networks (EDSN) bus as it uses the same software interface application, which was demonstrated in the previous task. This paper describes the design, integration and architecture of the proposed propulsion subsystem for a planned Technology Demonstration Mission. In addition, a general review of the Pulsed Plasma technology available for CubeSats is presented in order to assess the necessary challenges to overcome further development.

PCB↗
NASA NTRS1980

Internal electrostatic discharge hazard risk assessment to the Galileo orbiter

A worst case assessment was performed on the Command Data System (CDS) multilayer printed circuit board and an output power transformer module in the power subsystem. An estimate of the Jovian environment during the 35 hour orbit insertion was supplied by JPL and used as an input to calculate the electron transport into the Galileo components. A radiation shielding analysis computer code, CHARGE, calculated the electron transport deposition trapped in the anticipated sensitive areas of the multilayer board and transformer module. Based on these trapped charge calculations electric fields were calculated between the identified isolated areas and the spacecraft ground. The results of the assessment of electrostatic discharge (DSD) in the CDS multilayer printed circuit board indicate that the probability of ESD in the FR4 is low. The probability of ESD in the components attached to the multilayer board, however, is uncertain based on a lack of prior experimental data.

Schmidt, R. E.↗
NASA NTRS2012

Alumina Based 500 C Electronic Packaging Systems and Future Development

NASA space and aeronautical missions for probing the inner solar planets as well as for in situ monitoring and control of next-generation aeronautical engines require high-temperature environment operable sensors and electronics. A 96% aluminum oxide and Au thick-film metallization based packaging system including chip-level packages, printed circuit board, and edge-connector is in development for high temperature SiC electronics. An electronic packaging system based on this material system was successfully tested and demonstrated with SiC electronics at 500 C for over 10,000 hours in laboratory conditions previously. In addition to the tests in laboratory environments, this packaging system has more recently been tested with a SiC junction field effect transistor (JFET) on low earth orbit through the NASA Materials on the International Space Station Experiment 7 (MISSE7). A SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE7 suite to International Space Station via a Shuttle mission and tested on the orbit for eighteen months. A summary of results of tests in both laboratory and space environments will be presented. The future development of alumina based high temperature packaging using co-fired material systems for improved performance at high temperature and more feasible mass production will also be discussed.

Chen, Liang-Yu↗
NASA NTRS2015

Packaging Technologies for 500 C SiC Electronics and Sensors: Challenges in Material Science and Technology

This paper presents ceramic substrates and thick-film metallization based packaging technologies in development for 500C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550C. The 96 alumina packaging system composed of chip-level packages and PCBs has been successfully tested with high temperature SiC discrete transistor devices at 500C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC junction field-effect-transistor (JFET) with a packaging system composed of a 96 alumina chip-level package and an alumina printed circuit board was tested on low earth orbit for eighteen months via a NASA International Space Station experiment. In addition to packaging systems for electronics, a spark-plug type sensor package based on this high temperature interconnection system for high temperature SiC capacitive pressure sensors was also developed and tested. In order to further significantly improve the performance of packaging system for higher packaging density, higher operation frequency, power rating, and even higher temperatures, some fundamental material challenges must be addressed. This presentation will discuss previous development and some of the challenges in material science (technology) to improve high temperature dielectrics for packaging applications.

dielectric properties↗
NASA NTRS2013

Packaging Technologies for High Temperature Electronics and Sensors

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500degC silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chiplevel packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550degC. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500degC for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500degC are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Electronic packaging↗
NASA NTRS2013

Packaging Technologies for High Temperature Electronics and Sensors

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500 C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550 C. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500 C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500 C are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Chen, Liang-Yu↗
DOE OSTI2022

Conductive trace interconnection tape

A conductive trace interconnect tape for use with a printed circuit board or a flexible circuit substrate comprises a top insulating layer, an electrically conductive layer, and a bottom insulating layer. The top insulating layer is formed from electrically insulating material and is configured to provide electrical isolation from electrically conductive objects that are positioned on top of the conductive trace interconnect tape. The electrically conductive layer is positioned underneath the top insulating layer. The electrically conductive layer is formed from electrically conductive material and includes electrical interconnect traces, electrical component pads, or electrically conductive planar portions. The bottom insulating layer is positioned underneath the electrically conductive layer. The bottom insulating layer is formed from electrically insulating material and is configured to provide electrical isolation from electrically conductive objects that are positioned on the printed circuit board or flexible circuit substrate.

Hatch, Stephen McGarry↗
DOE OSTI2023

Conductive trace interconnection tape

A conductive trace interconnect tape for use with a printed circuit board or a flexible circuit substrate comprises a top insulating layer, an electrically conductive layer, and a bottom insulating layer. The top insulating layer is formed from electrically insulating material and is configured to provide electrical isolation from electrically conductive objects that are positioned on top of the conductive trace interconnect tape. The electrically conductive layer is positioned underneath the top insulating layer. The electrically conductive layer is formed from electrically conductive material and includes electrical interconnect traces, electrical component pads, or electrically conductive planar portions. The bottom insulating layer is positioned underneath the electrically conductive layer. The bottom insulating layer is formed from electrically insulating material and is configured to provide electrical isolation from electrically conductive objects that are positioned on the printed circuit board or flexible circuit substrate.

Hatch, Stephen McGarry↗
DOE OSTI2024

Ion Mobility Separations Using Cocentric Architecture

Ion mobility separations are usually performed in linear channels, which, when extended, can have a large footprint. In this work, we explored the performance of an ion mobility device with a curved architecture which can have a more compact form. The Co-centric Ion Mobility Spectrometer (CIMS) works by manipulating ions between two co-centric surfaces, each containing a serpentine track. The mobility separation inside CIMS is achieved using traveling waveforms (TWs). We initially evaluated the device using ion trajectory simulations using SIMION, which indicated that when ions traveled circularly inside CIMS, they resulted in similar resolving powers and transmitted m/z range as traveling in a straight path in structures for lossless ion manipulations (SLIM). We then performed experimental validation of CIMS in conjunction with a TOF MS. The CIMS was made of 2 flexible printed circuit board materials folded into concentric cylinders separated by a gap of 2.8 mm. The device was about 50 mm diameter × 152 mm long and provided 1.846 m of serpentine path length. Three sets of mixtures (Agilent tune mixture, tetraalkylammonium salts, and 8 peptide mixture) and four traveling waveform profiles (square, sine, triangle, and sawtooth) were used. The sawtooth TW profile produced a slightly higher resolving power for the Agilent tuning mixture and tetraalkylammonium ions. The average resolving power for Agilent tune mixture ions ranged from 37 (using sawtooth TW) to 27 (using square TW). For tetraalkylammonium ions, the average resolving powers ranged from 45 (sawtooth TW) to 31 (square TW). For the peptide mixture ions, the resolving power was similar among the four TW profiles and ranged from 51 to 56. The average percent error in TW CCS for the peptide mixture ions ranged was about 0.4%. In conclusion, the new device showed promising results for a device made of a flexible printed circuit board material, but improvements are needed to further increase the resolving power.

59 BASIC BIOLOGICAL SCIENCES↗
NASA NTRS2004

Multi-level Simulation of a Real Time Vibration Monitoring System Component

This paper describes the development of a custom built Digital Signal Processing (DSP) printed circuit board designed to implement the Advanced Real Time Vibration Monitoring Subsystem proposed by MSFC Transportation Directorate in 2000 for the Space Shuttle Main Engine Advanced Health Management System (AHMS). This Real Time Vibration Monitoring System (RTVMS) is being developed for ground use as part of the AHMS Health Management Computer-Integrated Rack Assembly (HMC-IRA). The HMC-IRA RTVMS design contains five DSPs which are highly interconnected through individual communication ports, shared memory, and a unique communication router that allows all the DSPs to receive digitized data from two multi-channel analog boards simultaneously. This paper will briefly cover the overall board design but will focus primarily on the state-of-the-art simulation environment within which this board was developed. This 16-layer board with over 1800 components and an additional mezzanine card has been an extremely challenging design. Utilization of a Mentor Graphics simulation environment provided the unique board and system level simulation capability to ascertain any timing or functional concerns before production. By combining VHDL, Synopsys Software and Hardware Models, and the Mentor Design Capture Environment, multiple simulations were developed to verify the RTVMS design. This multi-level simulation allowed the designers to achieve complete operability without error the first time the RTVMS printed circuit board was powered. The HMCIRA design has completed all engineering unit testing and the deliverable unit is currently under development.

Roberston, Bryan↗
NASA NTRS2005

Multi-level Simulation of a Real Time Vibration Monitoring System Component

This paper describes the development of a custom built Digital Signal Processing (DSP) printed circuit board designed to implement the Advanced Real Time Vibration Monitoring Subsystem proposed by Marshall Space Flight Center (MSFC) Transportation Directorate in 2000 for the Space Shuttle Main Engine Advanced Health Management System (AHMS). This Real Time Vibration Monitoring System (RTVMS) is being developed for ground use as part of the AHMS Health Management Computer-Integrated Rack Assembly (HMC-IRA). The HMC-IRA RTVMS design contains five DSPs which are highly interconnected through individual communication ports, shared memory, and a unique communication router that allows all the DSPs to receive digitized data fiom two multi-channel analog boards simultaneously. This paper will briefly cover the overall board design but will focus primarily on the state-of-the-art simulation environment within which this board was developed. This 16-layer board with over 1800 components and an additional mezzanine card has been an extremely challenging design. Utilization of a Mentor Graphics simulation environment provided the unique board and system level simulation capability to ascertain any timing or functional concerns before production. By combining VHDL, Synopsys Software and Hardware Models, and the Mentor Design Capture Environment, multiple simulations were developed to verify the RTVMS design. This multi-level simulation allowed the designers to achieve complete operability without error the first time the RTVMS printed circuit board was powered. The HMC-IRA design has completed all engineering and deliverable unit testing. P

Robertson, Bryan A.↗
DOE OSTI2022

Design optimization of an additively manufactured prototype recuperator for supercritical CO 2 power cycles

Supercritical CO 2 (sCO 2 ) power cycles are being developed due to their potential for high efficiency and reduced capital cost. It is necessary that these recuperators operate at high pressures and temperatures, up to 30 MPa and 900 K, with effectiveness values > 95% and pressure drops <1% to achieve high cycle efficiencies. Moreover, it is also necessary to have reasonable cost recuperators to control the capital costs of the sCO 2 power cycles. In this study, a Plate Pin-Fin (PPF) heat exchanger has been proposed as an sCO 2 recuperator. This preliminary recuperator design leverages capabilities enabled by additive manufacturing. Although the PPF design has characteristics similar to those of a plate heat exchanger, small diameter and relatively long fins are used to increase surface area, enhance heat transfer, and provide structural support for the partition plates that separate the fluid streams. Existing correlations for heat transfer and pressure drop were adapted for the PPF heat exchanger. These correlations were implemented in a 1D analytical model and used for the optimization of a 5-kW th high temperature recuperator for an indirect sCO 2 cycle by varying the design parameters to minimize the quantity of material required. A 3D conjugate heat transfer numerical simulations were conducted to validate the heat transfer and pressure loss correlations. A steepest descent method was used to minimize heat exchanger mass for a 5-kW prototype recuperator subject to a maximum specified pressure drop. Additionally, the design analysis indicated that an optimum PPF recuperator would be attained for the minimum allowable pin transverse spacing, minimum pin width, minimum pin height and near maximum cell aspect ratio. Moreover, at a low material requirement of 0.216 kg/kW and a pressure drop, which is almost five times lower than the allowable pressure drop design target, the optimized PPF heat exchanger has the high potential to be an alternative to a printed circuit heat exchanger, which is a conservative design basis for the current state-of-the-art sCO 2 recuperators.

42 ENGINEERING↗
NASA NTRS2016

Command and Data Handling Branch Internship

Modular Integrated Stackable Layers (MISL) is a computer system designed for simple, fast, and cost effective flexible reconfiguration in space environments such as the ISS and Orion projects for various uses. Existing applications include wireless and wired communications, data acquisition and instrumentation, and camera systems, and potential applications include bus protocol converters and subsystem control. MISL is based on Texas Instruments (TI)' MSP430 16-bit ultra-low-power microcontroller device. The purpose of my project was to integrate the MISL system with a liquid crystal display (LCD) touchscreen. The LCD, manufactured by Crystalfontz and part number CFAF320240F-035T-TS, is a 320 by 240 RGB resistive color screen including an optional carrier board. The vast majority of the project was done with Altium Designer, a tool for printed circuit board (PCB) schematic capture, 3D design, and FPGA (Field Programmable Gate Array) development. The new PCB was to allow the LCD to directly stack to the rest of MISL. Research was done with datasheets for the TI microcontroller and touchscreen display in order to meet desired hardware specifications. Documentation on prior MISL projects was also utilized. The initial step was to create a schematic for the LCD, power bus, and data bus connections between components. A layout was then designed with the required physical dimensions, routed traces and vias, power and ground planes, layer stacks, and other specified design rules such as plane clearance and hole size. Multiple consultation sessions were held with Hester Yim, the technical discipline lead for the Command and Data Handling Branch, and Christy Herring, the lead PCB layout designer in the Electronic Design and Manufacturing Branch in order to ensure proper configuration. At the moment, the PCB is awaiting revision by the latter-mentioned branch. Afterwards, the board will begin to undergo the manufacturing and testing process. Throughout the internship at Johnson Space Center, I gained several technical and professional skills. I gained proficiency in Altium Designer and experience using subversion clients, as well as knowledge in PSpice with OrCAD and battery design for spaceflight from on-site. I also gained networking, organization, and communication skills throughout meetings with coworkers and other interns. This internship at Johnson Space Center has impacted my future aspirations by further inspiring me to follow a career path into space rated engineering technology and human spaceflight applications. After graduation, I plan to attend graduate Modular Integrated Stackable Layers (MISL) is a computer system designed for simple, fast, and cost effective flexible reconfiguration in space environments such as the ISS and Orion projects for various uses. Existing applications include wireless and wired communications, data acquisition and instrumentation, and camera systems, and potential applications include bus protocol converters and subsystem control. MISL is based on Texas Instruments’ MSP430 16 bit ultra-low power microcontroller device. The purpose of my project was to integrate the MISL system with a liquid crystal display touchscreen. The LCD, manufactured by Crystalfontz and part number CFAF320240F-035T-TS, is a 320x240 RGB resistive color screen including an optional carrier board.The vast majority of the project was done with Altium Designer, a tool for printed circuit board (PCB) schematic capture, 3D design, and FPGA development. The new PCB was to allow the LCD to directly stack to the rest of MISL. Research was done with datasheets for the TI microcontroller and touchscreen display in order to meet desired hardware specifications. Documentation on prior MISL projects was also utilized. The initial step was to create a schematic for the LCD, power bus, and data bus connections between components. A layout was then designed with the required physical dimensions, routed traces and vias, power and ground planes, layer stacks, and other specified design rules such as plane clearance and hole size. Multiple consultation sessions were held with Hester Yim, the technical discipline lead for the Command and Data Handling Branch, and Christy Herring, the lead PCB layout designer in the Electronic Design and Manufacturing Branch in order to ensure proper configuration. At themoment, the PCB is awaiting revision by the latter-mentioned branch. Afterwards, the board will begin to undergo the manufacturing and testing process.Throughout the internship at Johnson Space Center, I gained several technical and professional skills. I gained proficiency in Altium Designer and experience using subversion clients, as well as knowledge in PSpice with OrCAD and battery design for spaceflight from on-site. I also gained networking, organization, and communication skills throughout meetings with coworkers and other interns. This internship at Johnson Space Center has impacted my future aspirations by further inspiring me to follow a career path into space rated engineering technology and human spaceflight applications. After graduation, I plan to attend graduate school for a master's or doctorate degree in electrical or computer engineering.

Billings, Rachel Mae↗
NASA NTRS1989

Advanced technology satellite demodulator development

Ford Aerospace has developed a proof-of-concept satellite 8 phase shift keying (PSK) modulation and coding system operating in the Time Division Multiple Access (TDMA) mode at a data range of 200 Mbps using rate 5/6 forward error correction coding. The 80 Msps 8 PSK modem was developed in a mostly digital form and is amenable to an ASIC realization in the next phase of development. The codec was developed as a paper design only. The power efficiency goal was to be within 2 dB of theoretical at a bit error rate (BER) of 5x10(exp 7) while the measured implementation loss was 4.5 dB. The bandwidth efficiency goal was 2 bits/sec/Hz while the realized bandwidth efficiency was 1.8 bits/sec/Hz. The burst format used a preamble of only 40 8 PSK symbol times including 32 symbols of all zeros and an eight symbol unique word. The modem and associated special test equipment (STE) were fabricated mostly on a specially designed stitch-weld board although a few of the highest rate circuits were built on printed circuit cards. All the digital circuits were ECL to support the clock rates of from 80 MHz to 360 MHz. The transmitter and receiver matched filters were square-root Nyquist bandpass filters realized at the 3.37 GHz i.f. The modem operated as a coherent system although no analog phase locked (PLL) loop was employed. Within the budgetary constraints of the program, the approach to the demodulator has been proven and is eligible to proceed to the next phase of development of a satellite demodulator engineering model. This would entail the development of an ASIC version of the digital portion of the demodulator, and MMIC version of the quadrature detector, and SAW Nyquist filters to realize the bandwidth efficiency.

Ames, Stephen A.↗
NASA NTRS1995

Ku-Band Data-Communication Adapter

Data-communication adapter circuit on single printed-circuit board serves as general-purpose interface between personal computer and satellite communication system. Designed as direct interface with Ku-band data-communication system for payloads on space shuttle, also used with any radio-frequency transmission systems. Readily installed in almost any personal computer via widely used Industry Standard Architecture (ISA) bus.

Schadelbauer, Steve↗
NASA NTRS2013

Demonstrating the Effect of Particle Impact Dampers on the Random Vibration Response and Fatigue Life of Printed Wiring Assemblies

In a recent experimental study, small Particle Impact Dampers (PID) were bonded directly to the surface of printed circuit board (PCB) or printed wiring assemblies (PWA), reducing the random vibration response and increasing the fatigue life. This study provides data verifying practicality of this approach. The measured peak strain and acceleration response of the fundamental out of plane bending mode was significantly attenuated by adding a PID device. Attenuation of this mode is most relevant to the fatigue life of a PWA because the local relative displacements between the board and the supported components, which ultimately cause fatigue failures of the electrical leads of the board-mounted components are dominated by this mode. Applying PID damping at the board-level of assembly provides mitigation with a very small mass impact, especially as compared to isolation at an avionics box or shelf level of assembly. When compared with other mitigation techniques at the PWA level (board thickness, stiffeners, constrained layer damping), a compact PID device has the additional advantage of not needing to be an integral part of the design. A PID can simply be bonded to heritage or commercial off the shelf (COTS) hardware to facilitate its use in environments beyond which it was originally qualified. Finite element analysis and test results show that the beneficial effect is not localized and that the attenuation is not due to the simple addition of mass. No significant, detrimental reduction in frequency was observed. Side-by-side life testing of damped and un-damped boards at two different thicknesses (0.070" and 0.090") has shown that the addition of a PID was much more significant to the fatigue life than increasing the thickness. High speed video, accelerometer, and strain measurements have been collected to correlate with analytical results.

Knight, Brent↗