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Results for “INTEGRATED CIRCUIT”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2018

Test circuits for integrated circuit counterfeit detection

Described herein are various technologies pertaining to identifying counterfeit integrated circuits (ICs) by way of allowing the origin of fabrication to be verified. An IC comprises a main circuit and a test circuit that is independent of the main circuit. The test circuit comprises at least one ring oscillator (RO) signal that, when energized, is configured to output a signal that is indicative of a semiconductor fabrication facility where the IC was manufactured.

42 ENGINEERING↗
DOE OSTI2019

Test circuits for integrated circuit counterfeit detection

Described herein are various technologies pertaining to identifying counterfeit integrated circuits (ICs) by way of allowing the origin of fabrication to be verified. An IC comprises a main circuit and a test circuit that is independent of the main circuit. The test circuit comprises at least one ring oscillator (RO) signal that, when energized, is configured to output a signal that is indicative of a semiconductor fabrication facility where the IC was manufactured.

Helinski, Ryan↗
DOE OSTI2020

Setting operating points for circuits in an integrated circuit chip using an integrated voltage regulator power loss model

An apparatus includes an integrated circuit chip with a set of circuits having two or more subsets of circuits; an external voltage regulator separate from the integrated circuit chip; two or more integrated voltage regulators on the integrated circuit chip that each provide an input voltage to a respective subset of the circuits; and a controller. The controller determines, using an integrated voltage regulator power loss model, an electrical power loss for the integrated voltage regulators for a first combination of operating points for the subsets of the circuits. The controller then determines, based on the electrical power loss, a second combination of operating points for the subsets of the circuits that includes an adjustment to an operating point for at least one of the subsets of the circuits that compensates for an electrical power loss of the corresponding integrated voltage regulator. The controller sets an operating point of each of the subsets of the circuits based on the second combination of operating points.

42 ENGINEERING↗
DOE OSTI2018

Setting operating points for circuits in an integrated circuit chip

The described embodiments include an apparatus that controls voltages for an integrated circuit chip having a set of circuits. The apparatus includes a switching voltage regulator separate from the integrated circuit chip and two or more low dropout (LDO) regulators fabricated on the integrated circuit chip. The switching voltage regulator provides an output voltage that is received as an input voltage by each of the two or more LDO regulators, and each of the two or more LDO regulators provides a local output voltage, each local output voltage received as a local input voltage by a different subset of the circuits in the set of circuits. During operation, a controller sets an operating point for each of the subsets of circuits based on a combined power efficiency for the subsets of the circuits and the LDO regulators, each operating point including a corresponding frequency and voltage.

42 ENGINEERING↗
DOE OSTI2019

Setting operating points for circuits in an integrated circuit chip

The described embodiments include an apparatus that controls voltages for an integrated circuit chip having a set of circuits. The apparatus includes a switching voltage regulator separate from the integrated circuit chip and two or more low dropout (LDO) regulators fabricated on the integrated circuit chip. The switching voltage regulator provides an output voltage that is received as an input voltage by each of the two or more LDO regulators, and each of the two or more LDO regulators provides a local output voltage, each local output voltage received as a local input voltage by a different subset of the circuits in the set of circuits. During operation, a controller sets an operating point for each of the subsets of circuits based on a combined power efficiency for the subsets of the circuits and the LDO regulators, each operating point including a corresponding frequency and voltage.

Huang, Wei↗
DOE OSTI2022

System-on-chip integrated circuit technology applications on the DIII-D tokamak for multi-field measurements

Several mm-wave diagnostics on the DIII-D tokamak provide multi-scale and multi-dimensional measurements of plasma profile evolution and turbulence fluctuations. Mm-wave fusion plasma diagnostics that adopt system-on-chip integrated circuit technology can provide better space utilization, flexible installation, and improved sensitivity. In order to further extend this technology for additional fusion facilities with a higher toroidal magnetic field, V-band (55–75 GHz) and F-band (90–140 GHz) chips for Microwave Imaging Reflectometer (MIR) and Electron Cyclotron Emission Imaging (ECEI) instruments are developed and tested in the Davis Millimeter Wave Research Center (DMRC). Current measurement data show that correlation between these SoC-based diagnostic instruments with other state-of-the-art diagnostics enables co-located multi-field turbulence fluctuation measurement.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2022

Economic and embodied energy analysis of integrated circuit manufacturing processes

Integrated circuits (ICs) are the fundamental microelectronic building blocks of typical information and communication technology (ICT) devices such as laptops and smartphone. With the emergence of faster and cheaper low-power ICs for the growing ICT market, there is a limited information on their manufacturing energy and economic impacts owing to the lack of recurrent upgradation of proprietary IC manufacturing process data. In this work, economic and life cycle energy assessments (LCAs) of IC manufacturing and assembly processes were conducted using the latest bill of materials (BOM) manufacturing data in a state-of-the-art IC manufacturing cost software tool developed by IC Knowledge, LLC. IC manufacturing cost was estimated to be $\$$1.00-$\$$5.00/cm 2 ; the high-end cost represents the most advanced 3D NAND IC technology with the Wafer Level Chip Scale Package cost of $4/cm 2 . Total cumulative energy demand (CED) estimates of IC manufacturing using the OpenLCA software ranged from 9 to 38 MJ/cm 2 or 56–235 BJ/month with the largest share (~ 75%) from on-site energy. The IC manufacturing CED is projected to increase with the progress in IC technology node, which has increased by more than two times for technology node evolution from 110 to 14 nm. Furthermore, the representative detailed BOM data were considered to reduce the CED uncertainties of the estimated standard deviation of 35%- 42%.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

Monolithic integrated quantum dot photonic integrated circuits

A photonic integrated circuit (PIC) includes a semiconductor substrate, one or more passive components, and one or more active components. The one or more passive components are fabricated on the semiconductor substrate, wherein the passive components are fabricated in a III-V type semiconductor layer. The one or more active components are fabricated on top of the one or more passive components, wherein optical signals are communicated between the one or more active components via the one or more passive components.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2023

Monolithic integrated quantum dot photonic integrated circuits

A photonic integrated circuit (PIC) includes a semiconductor substrate, one or more passive components, and one or more active components. The one or more passive components are fabricated on the semiconductor substrate, wherein the passive components are fabricated in a III-V type semiconductor layer. The one or more active components are fabricated on top of the one or more passive components, wherein optical signals are communicated between the one or more active components via the one or more passive components.

Bowers, John E.↗
DOE OSTI2023

Offset-aligned three-dimensional integrated circuit

A three-dimensional integrated circuit includes a first die structure having a first geometry. The first die structure includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The three-dimensional integrated circuit includes a second die structure having a second geometry. A stacked portion of the second die structure is aligned with the first region. The three-dimensional integrated circuit includes an additional die structure stacked with the first die structure and the second die structure. The additional die structure has the first geometry or the second geometry.

Wilkerson, Brett P.↗
DOE OSTI2020

Strain-engineered high-responsivity MoTe 2 photodetector for silicon photonic integrated circuits

In integrated photonics, specific wavelengths are preferred such as 1550 nm due to low-loss transmission and the availability of optical gain in this spectral region. For chip-based photodetectors, layered two-dimensional (2D) materials bear scientific and technologically relevant properties such as electrostatic tunability and strong light-matter interactions. However, no efficient photodetector in the telecommunication C-band has been realized with 2D transition metal dichalcogenide materials due to their large optical bandgap. Furthermore, we demonstrate a MoTe 2 -based photodetector featuring strong photoresponse (responsivity = 0.5 A/W -1 ) operating at 1550 nm in silicon photonics enabled by strain engineering the 2D material. Non-planarized waveguide structures show a locally-induced bandgap change of 0.2 eV inside MoTe 2 , resulting in large photo-response, in an otherwise photo-inactive medium when unstrained. Unlike Graphene-based photodetectors relying on a gapless band structure, this photodetector shows a ~100X improved dark current, enabling an efficient noise equivalent power of 90 pW/Hz -0.5 . Such strain-engineered integrated photodetector provides new opportunities for integrated optoelectronic systems.

47 OTHER INSTRUMENTATION↗
DOE OSTI2019

Input-output processing on a remote integrated circuit chip

An electronic device includes a first integrated circuit chip including a processing functional block, and a second integrated circuit chip including an input-output (IO) functional block. The IO functional block performs one or more IO processing operations on behalf of the processing functional block in the first integrated circuit chip. The first integrated circuit chip lacks at least some elements of the IO functional block, so that the processing functional block is unable to perform corresponding IO operations without the IO functional block.

42 ENGINEERING↗
DOE OSTI2020

Offset-aligned three-dimensional integrated circuit

A three-dimensional integrated circuit includes a first die having a first geometry. The first die includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The first die includes first electrical contacts disposed in the first region on a first side of the first die along a periphery of the first die. The three-dimensional integrated circuit includes a second die having a second geometry. The second die includes second electrical contacts disposed on a first side of the second die. A stacked portion of the second die is stacked within the periphery of the first die and an overhang portion of the second die extends beyond the periphery of the first die. The second electrical contacts are aligned with and coupled to the first electrical contacts.

42 ENGINEERING↗
DOE OSTI2022

Offset-aligned three-dimensional integrated circuit

A method for manufacturing a three-dimensional integrated circuit includes attaching a first side of a first die to a first carrier wafer. The method includes preparing a second side of the first die to generate a prepared second side of the first die. The method includes attaching the prepared second side of the first die to a second carrier wafer. The method includes removing the first carrier wafer from the first side of the first die to form a transitional three-dimensional integrated circuit. The method includes attaching a third carrier wafer to a first side of the transitional three-dimensional integrated circuit. The method includes attaching a first side of the second die to a second side of the transitional three-dimensional integrated circuit.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

Dimming LED circuit augmenting DC/DC controller integrated circuit

Embodiments include systems, methods, and apparatuses for providing a dimming function in a single stage AC input light emitting diode (LED) driver with a controller that contains an on-chip error amplifier and an on-chip fixed reference voltage source coupled to a first input of the error amplifier. The controller controls a duty cycle of a switching transistor to cause a feedback voltage, applied to a first package input terminal, to match the reference voltage. To achieve a dimming function, a voltage across a current sense resistor in series with the LEDs is applied to a first input of a high gain differential amplifier, and a variable dimming control voltage is applied to a second input of the differential amplifier. The output of the differential amplifier is coupled to the first package input terminal. The differential amplifier input signals will be matched at the target LED current level.

Song, Zhengrong↗
DOE OSTI2017

Method of making thermally-isolated silicon-based integrated circuits

Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

36 MATERIALS SCIENCE↗
DOE OSTI2017

Thermally-isolated silicon-based integrated circuits and related methods

Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

36 MATERIALS SCIENCE↗
DOE OSTI2026

Magnetic flux imaging in a 3D superconductor integrated circuit

We report on imaging magnetic flux distributions in a multilayered superconductor integrated circuit which emerge during magnetization and after field cooling of the circuit in the DC magnetic field. The obtained complicated field maps expose the flux propagation across the patterned superconducting ground planes sandwiching layers with Josephson junction-based logic cells, fine wire grid around the functional units, and multiple superconducting fill structures located in different inner layers. The observed intricate flux distributions are explained by specific patterns of Meissner screening currents and superconducting critical currents in different mutually interacting parts of the integrated circuit. Our results provide important insights into possible ways of improving the protection of superconductor integrated circuits from magnetic fields and their resilience against flux trapping.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗