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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2026

Magnetic flux imaging in a 3D superconductor integrated circuit

We report on imaging magnetic flux distributions in a multilayered superconductor integrated circuit which emerge during magnetization and after field cooling of the circuit in the DC magnetic field. The obtained complicated field maps expose the flux propagation across the patterned superconducting ground planes sandwiching layers with Josephson junction-based logic cells, fine wire grid around the functional units, and multiple superconducting fill structures located in different inner layers. The observed intricate flux distributions are explained by specific patterns of Meissner screening currents and superconducting critical currents in different mutually interacting parts of the integrated circuit. Our results provide important insights into possible ways of improving the protection of superconductor integrated circuits from magnetic fields and their resilience against flux trapping.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2025

Code Generators for Floating-Point Unit Design in Integrated Circuits (OpenFloat) v1.0

This IP provides a comprehensive set of code generators for various floating-point units (FPUs) essential for integrated circuit design and integration, targeting a broad spectrum of applications, including machine learning and scientific computing. The suite includes FP adders, multipliers, subtractors, dividers, reciprocals, exponentials, square roots, trigonometric functions (sine, cosine, arctangent), and more. It supports customizable hardware design parameters, such as precision (16, 32, 64, and 128 bits) and pipeline depths, offering users enhanced flexibility and productivity. The generated code is in an industry-standard hardware description language, ensuring compatibility with standard design flows, including simulation, verification, synthesis, and implementation on both field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs).

Shalf, JohnM. [Lawrence Berkeley National Laborato↗
DOE OSTI2024

SMART SiC Power ICs: Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (Final Technical Report)

This collaborative project was initiated with the goal of developing Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (SMART SiC Power ICs). In pursuit of this objective, innovative designs and fabrication processes were implemented, enabling the development of large-scale (>1 cm²) SiC Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits and high-voltage (400–600 V) lateral power MOSFETs (HV-LDMOS) on 150 mm 4H-SiC substrates. The resulting SMART SiC Power ICs are tailored to support a wide range of applications requiring diverse voltage and power levels, including automotive systems, industrial equipment, electronic data processing, energy harvesting, and power conditioning. To achieve the proposed ‘SMART’ technology for SiC ICs, the team focused on 1) the Development of highly scalable CMOS (with high channel mobilities for n-type and p-type MOSFETs), LDMOS (~600V, 10A rated), and IC technologies, 2) Establishment of a manufacturable process baseline in a production-grade-, 150mm, SiC fabrication facility, and 3) Demonstration of SMART SiC ICs. The project initially comprised of fabricating 5 lots. In lot 1 monolithic integration using a single process was achieved. Here, we were able to successfully accomplish Integrated HV NMOSFET with LV CMOS on N-epi/N+ Substrate. The HV NMOS demonstrated a Breakdown Voltage (BV) more than 600V. Circuit demonstration of CMOS was also another achievement from this lot. In lot 2, priority was in place for isolation and integration. Here we addressed the isolation concerns and integrated the HV NMOS and LV CMOS using the N-epi/P-epi/N+ substrate. Similar to the lot 1, we were able to achieve a BV of 600 V for HV NMOS. Optimized gate oxide process with high channel mobilities, better gate oxide reliability, development of SPICE models, successful ohmic process development, novel wafer area saving design layouts, P+ isolation schemes with channeling implantations and high temperature operational circuits demonstrations are some of the key highlights from lot 1 and lot2. In lot 3, discrete device performances of HV NMOS with a BV ~700V and reliable LV CMOS performances were achieved. Also, novel architectural solutions were successfully implemented to suppress the electric field crowding at the gate oxide for reliable operations. In lot 4, half bridge power driver ICs with a conversion efficiency of (target 90% to 95%) in the 1-5MHz switching frequency range for output power between 25 W to 3 kW have been included in. However, due to the unfortunate events of sudden foundry shutdown (SiCamore Semi) the processing of lot 4 wafers came to a complete stop (January 2024). Arrangements have recently been made to shift the fabrication to another foundry, General Electric Aerospace. The fabrication process now on course (as of December 2024). Characterizations are delayed due to this unfortunate circumstance. The proposed trench architectural-based devices and ICs (lot 5) underwent modifications from the original project proposal. This change was necessitated by limitations in the availability of trench-based processes at commercial production-grade fabrication facilities in the US. Apart from above achievements, a Process Development Kit (PDK) was successfully developed for planar type SiC CMOS/LDMOS.

42 ENGINEERING↗
DOE OSTI2024

Method of additively manufacturing an integrated circuit of an interconnect packaging structure

A method of manufacturing an interconnect packaging structure is provided. In one aspect, the method includes forming a first body defining a cavity around at least one integrated circuit using an additive manufacturing machine, depositing a conductive transmission line on the first body and electrically coupling the conductive transmission line and the at least one integrated circuit with a conductive interconnect.

Papapolymerou, Ioannis↗
DOE OSTI2026

Optical nanofiber testbeds for benchmarking membrane-waveguide photonic integrated circuit platforms toward on-chip quantum inertial sensing

Recent advances in cold atom interferometry with optical and magnetic atom guides have set the stage for quantum inertial sensors capable of operating in dynamic environments. In this work, we present three key innovations—evanescent-field (EF) atom guides, optical nanofiber testbeds, and membrane-waveguide photonic integrated circuit (PIC) platforms—to advance EF-guided atom interferometry. First, we demonstrate EF atom guides on optical nanofiber testbeds, which serve as performance benchmarks for our membrane-waveguide PIC platforms. Second, we achieve low-power (⁠ ~ 5 mW) guiding of freely moving, laser-cooled 133 Cs atoms in two-color, traveling-wave EF optical dipole traps at the novel, heat-efficient magic wavelengths of 793 and 937 nm (i.e., “793/937-nm EF atom guides”). Concurrently, we design and fabricate membrane-waveguide PIC platforms for these EF atom guides; in our prior work, we showed that these structures safely accommodate 4–6 times the required optical trap power under vacuum and enable dense cold atom generation via magneto-optical trapping in the vicinity of the optical wavguide for efficient loading. Third, we verify preserved atomic coherence via microwave fields and EF-coupled Doppler-free Raman beams; to our knowledge, this is the first report of coherence fringes driven by co-propagating EF-coupled Raman beams with only 150 nW of total optical power. By providing a direct comparison between optical nanofiber testbeds and membrane-waveguide PIC platforms, our results lay critical groundwork for the on-chip realization of EF-guided atom interferometry and the development of fully integrated, compact, lightweight, and low-power quantum accelerometers and gyroscopes.

Orozco, Adrian [Sandia National Laboratories (SNL-↗
DOE OSTI2025

Growth and structure of alpha-Ta films for quantum circuit integration

Tantalum films incorporated into superconducting circuits have exhibited low surface losses, resulting in long-lived qubit states. The remaining loss pathways originate in microscopic defects that manifest as two level systems (TLSs) at low temperatures. These defects limit performance, so careful attention to tantalum film structures is critical for optimal use in quantum devices. In this work, we investigate the growth of tantalum using magnetron sputtering on sapphire, Si, and photoresist substrates. In the case of sapphire, we present procedures for the growth of fully-oriented films with α-Ta [1 1 1]//Al2O3 [0 0 0 1] and α-Ta [1 −1 0]//Al2O3 [1 0 −1 0] orientational relationships and having residual resistivity ratio (RRR) ∼ 60 for 220 nm thick films. On Si, we find a complex grain texturing with Ta [1 1 0] normal to the substrate and RRR ∼ 30. We further demonstrate airbridge fabrication using Nb to nucleate α-Ta on photoresist surfaces. For the films on sapphire, resonators show TLS-limited quality factors of 1.3 ± 0.3 × 106 at 10 mK (for a waveguide gap and conductor width of 3 and 6 μm, respectively). Structural characterization using scanning electron microscopy, x-ray diffraction, low temperature transport, secondary ion mass spectrometry, and transmission electron microscopy reveal the dependence of residual impurities and screw dislocation density on processing conditions. The results provide practical insights into the fabrication of advanced superconducting devices including qubit arrays and guide future works on crystallographically deterministic qubit fabrication.

42 ENGINEERING↗
DOE OSTI2025

RD53 pixel readout integrated circuits for ATLAS and CMS HL-LHC upgrades

The RD53 collaboration has since 2013 developed new hybrid pixel detector chips with 50 × 50 μm2 pixels for the HL-LHC upgrades of the ATLAS and CMS experiments at CERN. A common architecture, design and verification framework has been developed to enable final pixel chips of different sizes to be designed, verified and tested to handle extreme hit rates of 3 GHz/cm2 (up to 12 GHz per chip) together with an increased trigger rate of 1 MHz and efficient readout of up to 5.12 Gbits/s per pixel chip. Tolerance to an extremely hostile radiation environment with 1 Grad over 10 years and induced SEU (Single Event Upset) rates of up to 100 upsets per second per chip have been major challenges to make reliable pixel chips. Three generations of pixel chips, and many specific mixed signal building blocks and radiation test chips, have been submitted and extensively tested to get to final production chips. The large, complex and high rate pixel chips have been developed with a strong emphasis on low power consumption together with a concurrent development and qualification of novel serial powering at chip, module and system level, to minimize detector material budget.

Alimonti, G↗
DOE OSTI2025

Ultra-high Bandwidth, Ultra-high Dynamic Range X-Ray Shock Characterization via Photonic Integrated Circuit

Nuclear weapon component assessment tests at the Z Machine rely on accurate X-ray yield measurements for model validation, design and analysis of component survivability, and source optimization. Yield measurement devices currently used do not provide the requisite certainty to enable accurate and efficient data analysis of test results, which leads to an increase in Z-shots required for evaluation, longer device development times, and higher operation costs. Additionally, current X-ray flux detectors lack high temporal resolution at the tails. Similarly, shock measurement techniques used for component assessment often lack the ability to spatially resolve wave behavior thereby limiting the ability to measure shock propagation dynamics needed to design the next generation of ND components. Here we present the development of a photonic micro-calorimeter and shock sensor consisting of meter-long waveguide spirals that are optomechanically coupled to X-ray absorbing layers to characterize yield and shock propagation at nanosecond timescales.

42 ENGINEERING↗
DOE OSTI2025

Delay-resolved spectroscopy in terahertz photonic circuits

Photonic integrated circuits incorporating intersubband transitions are ideal for mid-infrared and terahertz nanophotonics. However, the design of epitaxies has long been inhibited by two factors: the modest predictivity of ab initio theory and the absence of absolute intersubband gain and loss measurements under operating conditions. Existing measurements either yield inaccurate gain profiles or do not accurately assess dependence on frequency, bias, and temperature. Here, we present a delay-resolved absolute-referencing method for accurate gain evaluation without these limitations, addressing a long-standing challenge. By creating a photonic circuit that allows broadband pulses to traverse different lengths of a gain medium, we measure the absolute transmission of intersubband structures. Gain profiles match theoretical predictions at lower temperatures, with gain and dispersion clamping after lasing, and faster-than-expected degradation occurs at higher temperatures. Our approach provides a precise experimental evaluation of temperature-dependent gain performance and gives insight into optimizing temperature performance and frequency comb designs.

Optical spectroscopy↗
DOE OSTI2024

Strong Zero Modes in Integrable Quantum Circuits

It is a classic result that certain interacting integrable spin chains host robust edge modes known as strong zero modes (SZMs). In this Letter, we extend this result to the Floquet setting of local quantum circuits, focusing on a prototypical model providing an integrable Trotterization for the evolution of the XXZ Heisenberg spin chain. By exploiting the algebraic structures of integrability, we show that an exact SZM operator can be constructed for these integrable quantum circuits in certain regions of parameter space. Our construction, which recovers a well-known result by Paul Fendley in the continuous-time limit, relies on a set of commuting transfer matrices known from integrability, and allows us to easily prove important properties of the SZM, including normalizabilty. Our approach is different from previous methods and could be of independent interest even in the Hamiltonian setting. Furthermore, our predictions, which are corroborated by numerical simulations of infinite-temperature autocorrelation functions, are potentially interesting for implementations of the XXZ quantum circuit on available quantum platforms.

1-dimensional spin chains↗
DOE OSTI2024

Final Technical Report - Rapid Surface Microanalysis using a Low Temperature Plasma

This project focused on improving our current understanding and scientific knowledge in the area of plasma-surface interactions and plasma assisted material synthesis related to advanced microelectronics and nanotechnology. Current challenges include: controlling the interaction of Low Temperature Plasma (LTP) with a single layer of atoms to manufacture integrated circuits, continued miniaturization of integrated circuits, LTP processing of material surfaces and thin films to enable industrial scale fabrication of advanced microelectronics, synthesis of new materials, nanomaterials, nanotubes, and complex materials, Technology developed in this subtopic is of value to either (i) enable scans of surfaces (~1 sq. cm area) using various microscopies (electron, optical, other) at high resolution (micron or sub-micron resolution) rapidly (hours or days rather than years to complete a high-resolution scan of such a large surface area), or (ii) enable scans of surfaces (~1 sq. cm area) using various microscopies (electron, optical, other) at relatively low resolution rapidly, then apply algorithms to select spots for micron-scale imaging. Sputtering occurs when particles of a solid material are ejected from its surface by energetic particles from a plasma. While the degradation of the solid material and the subsequent deposition of the ejected material onto vulnerable surfaces are the usual subjects of sputtering studies, plasma science has yet to be combined with sputtering to create new diagnostics devices and systems. Small changes in the design of the plasma discharge device make it possible to create broad plasma beams for rapid scanning or small plasma beams to obtain the distribution of ejected elements with micron resolution. In the high-resolution use, the ion flux is extracted from the gas-discharge plasma and focused by a spherical emission surface to micron sizes onto the target specimen, providing very local sputtering and local elemental analysis. We call this “self-focusing”. The radiation from the excited and ionized sputtered atoms is recorded by a spectrometer through a window and fiberglass cable and analyzed with standard software packages used for optical glow discharge spectroscopy. Computer simulations of beam formation were used to verify and optimize the designs to be tested. A prototype was designed, constructed, and used to start experiments of beam formation.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2024

Internship Work Report

I worked on two projects during my summer internship at Sandia. My official title was “Intern - Mission Tech Electrical Eng./Computer Eng.- R&D Undergraduate Summer.” I worked at the central location, which is Albuquerque, New Mexico. The department you are placed in at Sandia doesn’t always correspond to the people you will be working with. For example, I only directly worked with one person from my department this summer. On one of my projects, I worked with a diverse team of engineers from many different departments. On my other project, I mainly worked with two departments, as the project had two distinct parts. As mentioned earlier, I worked on two projects during my summer at Sandia. The first project focused on a lightweight embedded controller in an advanced FPGA System-on-Chip for radar signal processing applications. The term “controller” refers to a hardware device that directs the flow of data between two entities. An FPGA is a reprogrammable integrated circuit (as opposed to an integrated circuit with one purpose). An FPGA was used on this project so in order to protype various ideas for our System-on-Chip. My role on the project was to implement designs on the fabric of the FPGA and design a state machine (written in C) for the processor. My second project was also heavily involved with embedded systems but had a different application. It focused on using a Newton-Raphson control algorithm to stabilize an inverted pendulum using a novel microcontroller. The pendulum dynamics were derived, and it was successfully simulated in MATLAB. I worked on integrating the microcontroller with the inverted pendulum machinery, and converting the Newton-Raphson control algorithm from MATLAB into C. The inverted pendulum was successfully stabilized using a simple PID controller and industry-standard microcontroller. The project is still ongoing, and the team is gearing up for more tests using the novel Newton-Raphson control algorithm and novel microcontroller

42 ENGINEERING↗
DOE OSTI2025

Aligned carbon nanotubes for 1,000x improvement in computing (CRADA Final Report)

As part of the Cyclotron Road program, the Aligned Carbon team worked to improve and bring to market their technology to manufacture carbon nanotubes (CNTs) for integrated circuits. There are multiple applications which can benefit from the use of CNT based transistors in integrated circuits, including high performance computing, RF data transmission, and biosensing. Each of these applications faces a problem of poor starting CNT material to come to market. Aligned Carbon offers material with the highest ceiling of performance based around a fully aligned, uniform, on-wafer growth of CNTs and our proprietary purification process to remove metallic CNTs leaving only the semi-conducting ones behind. Further, Aligned Carbon has been guided by scalable manufacturing processes that will fit seamlessly into the integrated circuit foundry model of chip fabrication.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Post-processing of phase change material in a zero-change commercial silicon photonic process

Integration of phase change material (PCM) with photonic integrated circuits can transform large-scale photonic systems by providing non-volatile control over phase and amplitude. The next generation of commercial silicon photonic processes can benefit from the addition of PCM to enable ultra-low power, highly reconfigurable, and compact photonic integrated circuits for large-scale applications. Despite all the advantages of PCM-based photonics, today’s commercial foundries do not provide them in their silicon photonic processes yet. We demonstrate the first-ever electrically programmable PCM device that is monolithically post-processed in a commercial foundry silicon photonics process using a few fabrication steps and coarse-resolution photolithography. These devices achieved 1.4 dB/μm of amplitude switching contrast using a thin layer of 12.5 nm GeSbTe in this work. We have also characterized the reconfiguration speed as well as repeatability of these devices over 20,000 switching cycles. Our solution enables non-volatile photonic VLSI systems that can be fabricated at low cost and high reliability in a commercial foundry process, paving the way for the development of non-volatile programmable photonic integrated circuits for a variety of emerging applications.

Optics↗
DOE OSTI2024

Tunable quantum emitters on large-scale foundry silicon photonics

Abstract Controlling large-scale many-body quantum systems at the level of single photons and single atomic systems is a central goal in quantum information science and technology. Intensive research and development has propelled foundry-based silicon-on-insulator photonic integrated circuits to a leading platform for large-scale optical control with individual mode programmability. However, integrating atomic quantum systems with single-emitter tunability remains an open challenge. Here, we overcome this barrier through the hybrid integration of multiple InAs/InP microchiplets containing high-brightness infrared semiconductor quantum dot single photon emitters into advanced silicon-on-insulator photonic integrated circuits fabricated in a 300 mm foundry process. With this platform, we achieve single-photon emission via resonance fluorescence and scalable emission wavelength tunability. The combined control of photonic and quantum systems opens the door to programmable quantum information processors manufactured in leading semiconductor foundries.

Larocque, Hugo (ORCID:000900095849780X)↗