Metalorganic Chemical Vapor Deposition Gallium Nitride with Fast Growth Rate for Vertical Power Device Applications
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Materials Science↗
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Modeling Needs for Power Semiconductor Devices and Power Electronics Systems: Preprint
As energy systems move towards wide-spread electrification, penetration of power semiconductor devices and power electronics continues to grow at a rapid pace. This paper attempts to review the state of the art in power semiconductor modeling and the existing state of modeling in general when in it comes to design of devices and systems. The modeling needs for semiconductor devices vary depending on the end goal, and the level of abstraction needed towards model formulation also changes with the size and complexity of system to be designed. Finally, key aspects of thermal design and modeling for power electronics are also discussed.
24 POWER TRANSMISSION AND DISTRIBUTION↗
Field-dependent carrier transport in implanted isolation region of GaN lateral power devices
Among GaN lateral power devices, with proper E-field management, the breakdown occurs in the device isolation region rather than the active region. In this paper, we investigate field-dependent carrier transport in the isolation structures. Isolation test structures with variations in buffer doping, un-intentionally doped (UID) GaN thickness, and implantation conditions were fabricated. Electrical characterization was performed over a wide range of voltage and temperature. With varying UID GaN thickness and buffer doping, the leakage current and breakdown characteristics remain the same for a specific implantation condition, indicating that the leakage conduction and breakdown are governed by the implanted GaN region. Analysis of the temperature-dependent I–V reveals that carrier transport in the implanted GaN can be well explained by hopping conduction, involving three distinctive regions of operation depending on the E-field. At low E-field, carrier transport is ohmic, consistent with variable range hopping, driven by thermal activation. At medium E-field, a field enhanced thermally activated hopping is observed, following σ ∼ σ(T)exp(E). At high E-field, activation-less hopping is visible, following σ ∼ exp(−1/E), which occurs above a critical E-field limited by localization length.
Sadek, Mansura (ORCID:0000000322588338)↗
Semiconductor power device including wire or ribbon bonds over device active region
A semiconductor power device including a base plate; an input lead; an output lead; a field effect transistor (FET) power die disposed over the base plate, wherein the FET power die includes a set of source fingers, a set of drain fingers, and a set of gate fingers disposed directly over an active region, wherein the gate fingers are configured to receive an input signal from the input lead, and wherein the FET power die is configured to process the input signal to generate an output signal at the drain fingers for routing to the output lead; and electrical conductors (wirebonds or ribbons) bonded to the source and/or drain directly over the active region of the FET power die. The electrical conductors produce additional thermal paths between the active region and the base plate for thermal management of the FET power die.
42 ENGINEERING↗
Probing unintentional Fe impurity incorporation in MOCVD homoepitaxy GaN: Toward GaN vertical power devices
Unintentional impurity incorporation in GaN drift layers represents a challenging issue that can limit their potential performance in vertical power devices. In this paper, we focus on studying the origins of Fe impurity incorporation in metal-organic chemical vapor deposition (MOCVD) grown GaN materials. Acting as a compensator in n-type GaN drift layers, Fe impurities can reduce the electron mobility in GaN and limit the lowest controllable doping level. Two sources, the sample cleaning process and growth susceptor, were identified as the main mechanisms of Fe incorporation in the MOCVD GaN growth process. It was found that solvent cleaning of the wafer can introduce significant Fe contamination at the growth interface, which would slowly be incorporated into the GaN epilayer, thus causing background Fe impurity as high as 10 17 cm -3 level. Moreover, the Fe impurity in the coating material on the susceptor can introduce additional Fe impurity during the growth process. Our studies revealed that the Fe impurity level could be significantly suppressed by more than two orders when an alternative cleaning process was used and the susceptor surface was fully covered by substrates. Characterization of the Fe impurity concentrations was performed via secondary ion mass spectrometry. The trap level (E C - 0.57) eV from deep-level transient spectroscopy that had previously been attributed to Fe confirmed the carrier compensation effect from Fe. Room temperature Hall mobility as high as 1007 cm 2 /V s was achieved on the MOCVD grown low-Fe GaN. Results from this work will provide guidance for achieving high purity GaN toward high performance GaN vertical power devices.
42 ENGINEERING↗
A Single Passive Gate-Driver for Series Connected Power Devices in DC Circuit Breaker Applications
This letter proposes a novel single passive gate driver solution based on passive devices to control series-connected power semiconductor devices for dc circuit breaker (DCCB) applications. The transient suppression devices (e.g., metal oxide varistors) are utilized to achieve natural voltage balancing among the series devices, while providing the discharge path of the gate capacitor of the upper devices. Here, the proposed method is very simple, cost effective and more compact compared with conventional voltage balancing method-based DCCBs. Besides, gate voltage oscillation during the voltage recovery process is mitigated by the addition of an extra gate capacitor. Simulation and experimental results are provided to verify the effectiveness of proposed method.
24 POWER TRANSMISSION AND DISTRIBUTION↗
Electric Drive Technologies Consortium (EDTC)/ Cost competitive, high-Performance, highly Reliable (CPR) Power Devices on 4H-SiC (Final Report)
4H-Silicon carbide (4H-SiC) is a wide bandgap semiconductor that offers superior material properties over silicon, including higher critical electric field, thermal conductivity, and electron saturation velocity. These advantages make 4H-SiC highly attractive for high-voltage, high-efficiency power electronics. However, realizing the full potential of SiC requires device technologies that are not only high-performing but also manufacturable and reliable under real-world operating conditions. This report summarizes the outcomes of a five-year R&D effort funded by the U.S. Department of Energy (DOE) under the Electric Drive Technologies Consortium (EDTC), focused on developing cost-competitive, high-performance, and highly reliable (CPR) power devices on 4H-SiC substrates. The program targeted scalable and manufacturable 1.2 kV-class SiC MOSFETs optimized for next-generation electric vehicles, renewable energy systems, and industrial power conversion. The project delivered transformative advancements in SiC power device performance and ruggedness. Particularly, Specific on-resistance (R on,sp ) was reduced by up to 37%, from ~4.0 m$\Omega \cdot$cm 2 in earlier designs to an industry-leading 2.40 m$\Omega \cdot$cm 2 , driven by optimized doping, refined JFET widths, and layout engineering. Breakdown voltages (BV) exceeded 1600 V, marking improvement over legacy baselines, and demonstrating the robustness of newly implemented junction profiles and edge terminations. Short-circuit withstand time (SCWT) saw a remarkable 4$\times$ increase, from ~2 $\mu$s to over 8 $\mu$s, achieved through the successful deployment of deep P-well structures (~1.8–2.0 $\mu$m) via channeling implantation. This innovative process breakthrough enabled precise junction formation without MeV-class implantation tools, reduced leakage under high field stress, and allowed even the shortest-channel devices (down to 0.3 $\mu$m) to achieve both high BV and excellent ruggedness—breaking the traditional trade-off between conduction efficiency and blocking capability. Several novel architectures pushed the performance envelope further. JBSFETs—featuring embedded Schottky portions—eliminated bipolar degradation and drastically reduced third-quadrant leakage, while Ladder MOSFETs introduced a clever orthogonal conduction path that achieved a 15.4% reduction in R on,sp over standard linear designs. Switching performance reached new benchmarks: short-channel devices showed a 31% reduction in total switching energy compared to 0.5 $\mu$m counterparts, while maintaining manageable gate drive requirements. Layout-optimized structures not only improved transconductance but also accelerated switching transitions, pointing to real-world benefits in converter-level efficiency. The devices also passed rigorous reliability validation. Stress-tested across TDDB, HTGB, HTRB, HVP, and burn-in, the devices screened under 30 V/10 hr and 43 V/1 s protocols consistently exhibited tighter lifetime distributions and long-term oxide robustness. These screening techniques proved effective in identifying latent defects and ensuring deployment-grade reliability. Meanwhile, advanced 3D TCAD simulations revealed and resolved electric field hotspots—particularly in HEXFET corners—where fields exceeding 4.8 MV/cm were mitigated through geometry-aware layout corrections. Overall, the results of this project demonstrate a manufacturable and scalable SiC power device platform that addresses key DOE performance targets for efficient, robust, and reliable 1.2kV 4H-SiC Power Devices. The developed technologies represent a meaningful step forward in the commercial readiness of high-voltage SiC solutions and provide a strong foundation for continued advancement in wide bandgap power electronics.
42 ENGINEERING↗
Heteroepitaxial growth of Ga2O3 on 4H-SiC by liquid-injection MOCVD for improved thermal management of Ga2O3 power devices
We report on the growth of monoclinic β- and orthorhombic κ-phase Ga2O3 thin films using liquid-injection metal-organic chemical vapor deposition on highly thermally conductive 4H-SiC substrates using gallium (III) acetylacetonate or tris(2,2,6,6-tetramethyl-3,5-heptanedionato) gallium (III). Both gallium precursors produced the β phase, while only the use of the latter led to growth of κ-Ga2O3. Regardless of the used precursor, best results for β-Ga2O3 were achieved at a growth temperature of 700 °C and O2 flows in the range of 600–800 SCCM. A relatively narrow growth window was found for κ-Ga2O3, and best results were achieved for growth temperatures of 600 °C and the O2 flow of 800 SCCM. While phase-pure β-Ga2O3 was prepared, κ-Ga2O3 showed various degrees of parasitic β phase inclusions. X-ray diffraction and transmission electron microscopy confirmed a highly textured structure of β- and κ-Ga2O3 layers resulting from the presence of multiple in-plane domain orientations. Thermal conductivities of 53 nm-thick β-Ga2O3 (2.13 + 0.29/−0.51 W/m K) and 45 nm-thick κ-Ga2O3 (1.23 + 0.22/−0.26 W/m K) were determined by transient thermoreflectance and implications for device applications were assessed. Presented results suggest great potential of heterointegration of Ga2O3 and SiC for improved thermal management and reliability of future Ga2O3-based high power devices.
Materials Science↗
Tubular wave power device
A tubular wave energy converter configured to remain afloat near the surface of a wave field and trap a water column oscillating asymmetrically to the wave field in which the converter is located. Water column oscillations create a pressure flux providing motive power for a generator. The converter, generator and a powered payload making up an autonomous wave powered device are packaged to fit within and be deployed by a torpedo launcher. The autonomous device may be deployed above or beneath the surface. Device buoyant characteristics are configured to maintain the device afloat and self-righting toward an upright oriented for operation in the wave field.
Korde, Umesh↗
Plasma-based edge terminations for gallium nitride power devices
A p-n diode includes a first electrode, a n-GaN layer on the first electrode, a p-GaN layer on the n-GaN layer, and a second electrode on a first portion of the p-GaN layer. A region of the p-GaN layer surrounding the electrode is a passivated region. Treating a GaN power device having a p-GaN layer includes covering a portion of the p-GaN layer with a metal layer, exposing the p-GaN layer to a hydrogen plasma, and thermally annealing the p-GaN layer, thereby passivating a region of the p-GaN layer proximate the metal layer.
Zhao, Yuji↗
GaN MOCVD Growth on Native substrates for High Voltage (15-20 KV) Vertical Power Devices
This project aims to develop metalorganic chemical vapor deposition (MOCVD) homoepitaxy of GaN on native substrates with fast growth rate (15-20 μm/hr), low background doping (low-10 15 cm -3 ) and smooth surface morphology via comprehensive understanding of the crystal growth process including high quality GaN substrate development and surface preparation, impurity and native defects control, and their impacts on the breakdown field. The team successfully developed a new growth process by introducing the laser-assisted MOCVD (LA-MOCVD) process to address the limited growth rates of GaN in the traditional MOCVD process. Specifically, the use of the CO2 laser with lasing wavelength of 9.219 μm, the strong coupling between the laser beam with the ammonia (GaN MOCVD precursor) leads to efficient decomposition of NH3 which significantly increases the effective group V/III molar ratio and thus suppresses C impurity incorporation in MOCVD GaN. The reduction in C incorporation in LA-MOCVD GaN is especially prominent when the GaN growth rate is fast (> 10 μm/hr), which allows to develop thick GaN films with high crystalline quality and low controllable doping needed for vertical high power device applications. The results of this project lead to the demonstration of vertical GaN PN diodes with record breakdown voltage of ~ 8kV with high Baliga’s figure of merit.
24 POWER TRANSMISSION AND DISTRIBUTION↗
X-ray topography characterization of gallium nitride substrates for power device development
Gallium nitride substrates grown by the hydride vapor phase epitaxy (HVPE) method using a patterned growth process have been characterized by synchrotron monochromatic beam X-ray topography in the grazing incidence geometry. Images reveal a starkly heterogeneous distribution of dislocations with areas as large as 0 3 mm 2 containing threading dislocation densities below 10 3 cm -2 in between a grid of strain centers with higher threading dislocation densities (> 10 4 cm -2 ). Basal plane dislocation densities in these areas are as low as 104 cm -2 . By comparing the recorded images of dislocations with ray tracing simulations of expected dislocations in GaN, the Burgers vectors of the dislocations have been determined. The distribution of threading screw/mixed dislocations (TSDs/TMDs), threading edge dislocations (TEDs) and basal plane dislocations (BPDs) is discussed with implications for fabrication of power devices.
36 MATERIALS SCIENCE↗
Designing Ta C Virtual Substrates for Vertical Al x Ga 1 − x N Power Electronics Devices
Power electronics are critical for a sustainable energy future, playing a key role in electrification and integration of renewable energy sources into the grid. Advances in ultrawide band gap materials are needed to handle higher powers in smaller form factors while reducing electrical and thermal losses. High Al content Al x Ga 1 − x N is theoretically capable of meeting these demands, but its impact in power electronics has been severely restricted by a lack of substrates that can satisfy conductivity, lattice matching, and/or thermal expansion requirements. We demonstrate that electrically conductive Ta C can be used as a virtual substrate for Al x Ga 1 − x N heteroepitaxy. Scaleably sputtered Ta C grown on Al 2 O 3 , followed by high-temperature face-to-face annealing, produces a thin film Ta C template with an effective hexagonal lattice constant matched to Al 0.70 Ga 0.30 N . Annealing of the Ta C promotes recrystallization, significantly improving crystallinity and reducing crystalline defects from as-deposited columnar grains to a step-and-terrace surface morphology, enabling the subsequent growth of high-quality Al 0.70 Ga 0.30 N by molecular beam epitaxy. X-ray diffraction and scanning transmission electron microscopy confirm that the Al x Ga 1 − x N layer is heteroepitaxially aligned, strain-free, and lattice-matched, transitioning abruptly from Ta C to Al x Ga 1 − x N without intermediate phases. These results demonstrate Ta C virtual substrates as electrically conductive, lattice-matched, and thermally compatible templates for vertical Al x Ga 1 − x N devices that can meet the growing power needs of a sustainable energy future. Published by the American Physical Society 2024
36 MATERIALS SCIENCE↗
Top Stack Optimization for Cu 2 BaSn(S, Se) 4 Photovoltaic Cell Leads to Improved Device Power Conversion Efficiency beyond 6%
Earth-abundant and air-stable Cu 2 BaSnS 4-x Se x (CBTSSe) and related thin-film absorbers are regarded as prospective options to meet the increasing demand for low-cost solar cell deployment. Devices based on vacuum-deposited CBTSSe absorbers have achieved record power conversion efficiency (PCE) of 5.2 % based on a conventional device structure using CdS buffer and i-ZnO/ITO window layers, with open-circuit voltage (V OC ) posing the major bottleneck for improving solar cell performance. The current study demonstrates a >20 % improvement in V OC (from 0.62 V to 0.75 V) and corresponding enhancement in PCE (from 5.1 % to 6.2 % without anti-reflection coating; to 6.5 % with MgF 2 anti-reflection coating) for solution-deposited CBTSSe solar cells. This performance improvement is realized by introducing an alternative successive ionic layer adsorption and reaction (SILAR)-deposited Zn 1-x Cd x S buffer combined with sputtered Zn 1-x Mg x O/Al-doped ZnO window/top contact layer, which offer lower electron affinities relative to the conventional CdS/i-ZnO/ITO stack and better matching with the low electron affinity of CBTSSe. A combined experimental (temperature- and light intensity-dependent V OC measurements) and device simulation (SCAPS-1D) evaluation points to the importance of addressing relative band offsets for both the buffer and window layers relative to the absorber in mitigating interfacial recombination and optimizing CBTSSe solar cell performance.
25 ENERGY STORAGE↗
Unveiling the influence of selective-area-regrowth interfaces on local electronic properties of GaN p-n junctions for efficient power devices
Here, we report correlated nanoscale mapping of the structure, composition, and properties of regrown GaN p-n junctions to identify how etching and non-planar regrowth processes limit diode performance via the introduction of unintentional dopants and defect states. p-GaN was selectively regrown in n-GaN trenches with SiO 2 masks of variable mask-to-trench-width ratio. Dilute Al layers were periodically introduced during regrowth as markers of the growth interface. Correlated nanoscale mapping of doping, conductivity, and dopant complexes was achieved with atom probe tomography (APT), scanning spreading resistance microscopy (SSRM), and cathodoluminescence (CL) spectroscopy, respectively. The Al marker layers, detected by APT, enabled reconstruction of the faceted growth interface and correlation of the dopant concentration with position and time. The p-GaN growth rate is proportional to the mask-to-trench width ratio while the dopant incorporation rate is invariant. At trench edges, magnesium incorporation is suppressed, and oxygen incorporation enhanced, due to preferential incorporation on the semi-polar growth surface, leading to compensation and less abrupt p-n junctions; the SiO 2 mask is a source of oxygen. Residual etch damage below the regrowth interface induces n-type and p-type conductivity, creating leakage pathways. The non-uniform Mg incorporation is driven by crystal anisotropy and is thus inherent to non-planar regrowth, but can be mitigated by engineering the regrowth interface and process parameters. The unprecedented integration of spatially resolved mapping of dopants, impurities, conductivity, and carrier type is a powerful approach to discriminating distinct factors that limit the performance of regrown diodes, enabling the rational optimization of process and device design.
36 MATERIALS SCIENCE↗
Advanced Micro Combined Heat and Power Device
U.S. buildings account for approximately 40% of total U.S. energy consumption and 75% of electricity use, emphasizing the need for efficient, resilient, and secure energy solutions. Micro-combined heat and power (micro-CHP) systems provide an effective approach by simultaneously generating electricity and recovering waste heat for thermal use. However, current commercial micro-CHPs face challenges in achieving higher efficiency, lower emissions, and reduced cost. To address these limitations, a novel micro-CHP prototype powered by a unique opposed-piston four-stroke (OP4S) engine was developed. The OP4S features a simplified, low-cost design with reduced heat losses and dual-piston operation that enables higher thermal efficiency. Experimental results demonstrated up to 35.2% AC electrical efficiency under lean combustion, surpassing the best-performing ICE-based micro-CHPs reported publicly. In addition, the micro-CHP enables a total CHP efficiency exceeding 93%. The prototype operates reliably for over 600 hours, providing flexible and efficient thermal and electrical outputs. This novel OP4S-based micro-CHP offers a resilient, low-cost, and energy-efficient solution suitable for residential, light commercial, and remote community applications across diverse climate zones.
Gao, Zhiming [ORNL] (ORCID:0000000271397995)↗
Thermal Transport and Mechanical Stress Mapping of a Compression Bonded GaN/Diamond Interface for Vertical Power Devices
Bonding diamond to the back side of gallium nitride (GaN) electronics has been shown to improve thermal management in lateral devices; however, engineering challenges remain with the bonding process and characterizing the bond quality for vertical device architectures. Here, in this study, integration of these two materials is achieved by room-temperature compression bonding centimeter-scale GaN and a diamond die via an intermetallic bonding layer of Ti/Au. Recent attempts at GaN/diamond bonding have utilized a modified surface activation bonding (SAB) method, which requires Ar fast atom bombardment immediately followed by bonding within the same tool under ultrahigh vacuum (UHV) conditions. The method presented here does not require a dedicated SAB tool yet still achieves bonding via a room-temperature metal–metal compression process. Imaging of the buried interface and the total bonding area is achieved via transmission electron microscopy (TEM) and confocal acoustic scanning microscopy (C-SAM), respectively. The thermal transport quality of the bond is extracted from spatially resolved frequency-domain thermoreflectance (FDTR) with the bonded areas boasting a thermal boundary conductance of >100 MW/m 2 ·K. Additionally, Raman maps of GaN near the GaN–diamond interface reveal a low level of compressive stress, <80 MPa, in well-bonded regions. FDTR and Raman were coutilized to map these buried interfaces and revealed some poor thermally bonded areas bordered by high-stress regions, highlighting the importance of spatial sampling for a complete picture of bond quality. Overall, this work demonstrates a novel method for thermal management in vertical GaN devices that maintains low intrinsic stresses while boasting high thermal boundary conductances.
Raman↗