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One of the Lick Observatory Polaris telescopes was used to test seeing conditions at Mt. Lemmon. The preliminary results indicate that the seeing is not unlike that at Kitt Peak. Soundings of the air flow patterns across Mt. Lemmon under winter conditions were also made by flying smoke pots on tethered ballons to elevations of 500 feet. There does not appear to be any serious local turbulence.
This is a course on SEE Test Plan development. It is an introductory discussion of the items that go into planning an SEE test that should complement the SEE test methodology used. Material will only cover heavy ion SEE testing and not proton, LASER, or other though many of the discussed items may be applicable. While standards and guidelines for how-to perform single event effects (SEE) testing have existed almost since the first cyclotron testing, guidance on the development of SEE test plans has not been as easy to find. In this section of the short course, we attempt to rectify this lack. We consider the approach outlined here as a "living" document: mission specific constraints and new technology related issues always need to be taken into account. We note that we will use the term "test planning" in the context of those items being included in a test plan.
Ever since the closure of the Indiana University Cyclotron Facility (IUCF) in 2014, there has been an increasing use of medical proton therapy facilities (MPTF) for SEE testing with protons in the 200 MeV or greater regime. This talk covers some of the unique features and considerations for utilizing MPTFs including both logistical and technical aspects. This presentation provides an overview of lessons learned for SEE testing at MPTFs.
While standards and guidelines for performing SEE testing have existed for several decades, guidance for developing SEE test plans has not been as easy to find. In this presentation, the variety of areas that need to be considered ranging from resource issues (funds, personnel, schedule) to extremely technical challenges (particle interaction and circuit application), shall be discussed. Note: we consider the approach outlined here as a "living" document: Mission-specific constraints and new technology related issues always need to be taken into account.
Believe it or not, this has been a simplistic look at starting a checklist for SEE testing. Given a memory that has 68 operating modes, when a SEU occurs that changes the mode, just how do you determine what's going on? Laser and microbeam tests can help, but not easily for modern packaged devices. Expanding this approach to other more complex devices such as ADCs or processors as well as analog devices should be considered. The recommendation is to use the existing text standards as the starting point. Just make your own checklist for the device/technology/issues being considered. At HEART 2007, we presented some of the burgeoning challenges associated with single event effect(SEE) testing of modern commercial memories: a) Package, device complexity, test fixture, and data analysis issues were discussed; b) "Complete" SEE Characterization would take 15 years; c) Qualification test costs have a greater than 4 times increase over the last decade. In this talk, we continue to explore the roles of technology with an emphasis on the existing SEE Test Procedures and some of the concerns related to modern devices. The primary objective of the briefing is to provide some overarching guidance concerning the many considerations involved in the formulation of a SEE test plan provided in a " Checklist" format.we note that there is no such thing as a complete check list and that the best approach is to develop a flexible test plan that takes into account the device type and functions, the device technology, circuit and package design, and, of course, test facility and beam characteristics.
SEE test results are presented for proton, neutron, and heavy ion testing of the Qualcomm Snapdragon 820 and its support DDR4 device (in this case the SK Hynix 24 Gb LP DDR4 device H9HKNNNDGUMUBR-NMH). Processor crashes and DDR4 stuck bits are the primary SEE types for protons and neutrons. Test preparation difficulties and software limitations caused test efforts to be limited to processor crashes, SEFIs and SBU, and Stuck Bits in the DDR4 device. Interpretation of results is complicated by mixing of errors between devices.
The following are updated or new subjects added to the FPGA SEE Test Guidelines manual: academic versus mission specific device evaluation, single event latch-up (SEL) test and analysis, SEE response visibility enhancement during radiation testing, mitigation evaluation (embedded and user-implemented), unreliable design and its affects to SEE Data, testing flushable architectures versus non-flushable architectures, intellectual property core (IP Core) test and evaluation (addresses embedded and user-inserted), heavy-ion energy and linear energy transfer (LET) selection, proton versus heavy-ion testing, fault injection, mean fluence to failure analysis, and mission specific system-level single event upset (SEU) response prediction. Most sections within the guidelines manual provide information regarding best practices for test structure and test system development. The scope of this manual addresses academic versus mission specific device evaluation and visibility enhancement in IP Core testing.
The objective of this coarse Single Event Effect (SEE) test is to determine the suitability of the commercial Virtex-II Pro family for use in spaceflight applications. To this end, this test is primarily intended to determine any Singe Event Latchup (SEL) susceptibilities for these devices. Secondly, this test is intended to measure the level of Single Event Upset (SEU) susceptibilities and in a general sense where they occur. The coarse SEE test was performed on a commercial XC2VP7 device, a relatively small single processor version of the Virtex-II Pro. As the XC2VP7 shares the same functional block design and fabrication process with the larger Virtex-II Pro devices, the results of this test should also be applicable to the larger devices. The XC2VP7 device was tested on a commercial Virtex-II Pro development board. The testing was performed at the Cyclotron laboratories at Texas A&M and Michigan State Universities using ions of varying energy levels and fluences.
This viewgraph presentation reviews the Single Event Effects (SEE) testing of the Phillips SA8016BW 2.5 GHz Synthesizer that was chose by the GLAST Program for Frequency Generation. Included in this are diagrams of the phased-locked loop (PLL), the synthesizer, and heater.
This presentation will discuss the considerations an engineer should take to perform Single Event Effects (SEE) testing on GPU devices. Notable topics will include setup complexity, architecture insight which permits cross platform normalization, acquiring a reasonable detail of information from the test suite, and a few lessons learned from preliminary testing.
In this presentation, the driving factors changing the world of single-event effects (SEE) testing will be discussed. This includes both semiconductor technological advances and morphing space system philosophies. Considerations for meeting these new challenges will then follow.
This presentation will document the current state of high energy (>200 MeV) proton access in the U.S. for Single Event Effects (SEE) testing. This is continuation of efforts since the shutdown of the Indiana University Cyclotron Facility (IUCF).
We present the results of SEE testing with high energy protons and with low and high energy heavy ions. This paper summarizes test results for components considered for Low Earth Orbit and Deep Space applications.
Understanding the effects of the space environment on materials and systems is fundamental and essential for mission success. If not properly understood and designed for, the space environment can lead to materials degradation, reduction of functional lifetime, and system failure. Ground based testing is critical in predicting performance NASA/MSFC's expertise and capabilities make up the most complete SEE testing capability available.
In this presentation, the driving factors changing the world of single-event effects (SEE) testing will be discussed. This includes both semiconductor technological advances and morphing space system philosophies. Considerations for meeting these new challenges will then follow.
With challenges related to testing highly complex integrated circuits as well as entire systems continuing to grow, the use of higher energy heavy ions for single-event effects (SEE) testing becomes a critical technical need. This presentation, however, focuses only partially on the technical side with the main emphasis on the economics of using a high-energy heavy ion beam and comparing via notional cost models for testing.
ARM processors power a class of high-performance, lower power system on a chip devices. In the absence of radiation effects, these devices are highly desirable for space use. The processor core architecture for ARM devices is licensed to provide computing on multiple hardware platforms. The A5 processor is in a unique pioneering space for providing detailed radiation response data to explore the baseline performance of these devices. These data can help set options for ARM processors and possibly impact design choices for the next generation of ARM fault tolerance capabilities. The SAMA5D3 was tested to establish general SEE performance for a relatively simple implementation of the ARM A5 core. This testing observed SRAM sensitivity starting at an LET of about 3 MeV-cm2/mg, with a saturated cross section of about 2x10-8cm2/bit, and this was determined by both active write and read of the caches, in addition to the use of a debugger to provide test results. Crash/SEFI data was collected using both Linux and bare metal C-code. The onset LET for crashes was about LET 1.5 MeV-cm2/mg, with saturated cross sections of about 2x10-5 cm2 for bare metal (low utilization), and 2x10-4cm2 for Linux (high utilization) tests.
The use of complex single and multicore processors with significant cache memory, on-chip peripherals, memory controllers, and high speed input/output (IO) that integrate many of the parts of a traditional computer system is becoming more common in space applications. Such devices are often referred to as system on a chip devices (SOCs), even though the term is used somewhat inaccurately due to the lack of analog and mixed signal subcircuits. These devices are complex combinations of single- or multi-core processors with memory controllers, high-speed input/output (IO), and other peripheral structures that formerly would have been handled by off-chip resources. In the past the processors were tested for single event effects (SEE) separately, and the peripherals were often put into custom application-specific integrated circuits (ASICs) along with other resources required by the user. Performance and cost pressures have pushed commercial devices to incorporate many of the functional blocks into a single chip, an SOC. The NASA Electronic Parts and Packaging Program (NEPP) has been examining ways to perform SEE radiation hardness assurance (RHA) testing of these processor-centric SOCs to achieve reasonable understanding of their performance in space missions.