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At least 19 records

Analyzing System on A Chip Single Event Upset Responses using Single Event Upset Data, Classical Reliability Models, and Space Environment Data

We are investigating the application of classical reliability performance metrics combined with standard single event upset (SEU) analysis data. We expect to relate SEU behavior to system performance requirements. Our proposed methodology will provide better prediction of SEU responses in harsh radiation environments with confidence metrics. single event upset (SEU), single event effect (SEE), field programmable gate array devises (FPGAs)

single event effect (SEE)

Effects of space radiation on electronic microcircuits

The single event effects or phenomena (SEP), which so far have been observed as events falling on one or another of the SE classes: Single Event Upset (SEU), Single Event Latchup (SEL) and Single Event Burnout (SEB), are examined. Single event upset is defined as a lasting, reversible change in the state of a multistable (usually bistable) electronic circuit such as a flip-flop or latch. In a computer memory, SEUs manifest themselves as unexplained bit flips. Since latchup is in general caused by a single event of short duration, the single event part of the SEL term is superfluous. Nevertheless, it is used customarily to differentiate latchup due to a single heavy charged particle striking a sensitive cell from more ordinary kinds of latchup. Single event burnout (SEB) refers usually to total instantaneous failure of a power FET when struck by a single particle, with the device shorting out the power supply. An unforeseen failure of these kinds can be catastrophic to a space mission, and the possibilities are discussed.

Kolasinski, W. A.

Experimental determination of single-event upset (SEU) as a function of collected charge in bipolar integrated circuits

Single-Event Upset (SEU) in bipolar integrated circuits (ICs) is caused by charge collection from ion tracks in various regions of a bipolar transistor. This paper presents experimental data which have been obtained wherein the range-energy characteristics of heavy ions (Br) have been utilized to determine the cross section for soft-error generation as a function of charge collected from single-particle tracks which penetrate a bipolar static RAM. The results of this work provide a basis for the experimental verification of circuit-simulation SEU modeling in bipolar ICs.

Zoutendyk, J. A.

Single-Event Upset (SEU) model verification and threshold determination using heavy ions in a bipolar static RAM

Single-Event Upset (SEU) response of a bipolar low-power Schottky-diode-clamped TTL static RAM has been observed using Br ions in the 100-240 MeV energy range and O ions in the 20-100 MeV range. These data complete the experimental verification of circuit-simulation SEU modeling for this device. The threshold for onset of SEU has been observed by the variation of energy, ion species and angle of incidence. The results obtained from the computer circuit-simulation modeling and experimental model verification demonstrate a viable methodology for modeling SEU in bipolar integrated circuits.

Zoutendyk, J. A.

Empirical modeling of Single-Event Upset (SEU) in NMOS depletion-mode-load static RAM (SRAM) chips

A detailed experimental investigation of single-event upset (SEU) in static RAM (SRAM) chips fabricated using a family of high-performance NMOS (HMOS) depletion-mode-load process technologies, has been done. Empirical SEU models have been developed with the aid of heavy-ion data obtained with a three-stage tandem van de Graaff accelerator. The results of this work demonstrate a method by which SEU may be empirically modeled in NMOS integrated circuits.

Zoutendyk, J. A.

A guideline for heavy ion radiation testing for Single Event Upset (SEU)

A guideline for heavy ion radiation testing for single event upset was prepared to assist new experimenters in preparing and directing tests. How to estimate parts vulnerability and select an irradiation facility is described. A broad brush description of JPL equipment is given, certain necessary pre-test procedures are outlined and the roles and testing guidelines for on-site test personnel are indicated. Detailed descriptions of equipment needed to interface with JPL test crew and equipment are not provided, nor does it meet the more generalized and broader requirements of a MIL-STD document. A detailed equipment description is available upon request, and a MIL-STD document is in the early stages of preparation.

Nichols, D. K.

Single event upset (SEU) of semiconductor devices - A summary of JPL test data

The data summarized describe single event upset (bit-flips) for 60 device types having data storage elements. The data are from 15 acceleration tests with both protons and heavier ions. Tables are included summarizing the upset threshold data and listing the devices tested for heavy ion induced bit-flip and the devices tested with protons. With regard to the proton data, it is noted that the data are often limited to one proton energy, since the tests were usually motivated by the engineering requirement of comparing similar candidate devices for a system. It is noted that many of the devices exhibited no upset for the given test conditions (the maximum fluence and the maximum proton energy Ep are given for these cases). It is believed, however, that some possibility of upset usually exists because there is a slight chance that the recoil atom may receive up to 10 to 20 MeV of recoil energy (with more energy at higher Ep).

Nichols, D. K.

Non Radiation Hardened Microprocessors in Spaced Based Remote Sensing Systems

The CALIPSO (Cloud-Aerosol Lidar and Infrared Pathfinder Satellite Observations) mission is a comprehensive suite of active and passive sensors including a 20Hz 230mj Nd:YAG lidar, a visible wavelength Earth-looking camera and an imaging infrared radiometer. CALIPSO flies in formation with the Earth Observing System Post-Meridian (EOS PM) train, provides continuous, near-simultaneous measurements and is a planned 3 year mission. CALIPSO was launched into a 98 degree sun synchronous Earth orbit in April of 2006 to study clouds and aerosols and acquires over 5 gigabytes of data every 24 hours. The ground track of one CALIPSO orbit as well as high and low intensity South Atlantic Anomaly outlines is shown. CALIPSO passes through the SAA several times each day. Spaced based remote sensing systems that include multiple instruments and/or instruments such as lidar generate large volumes of data and require robust real-time hardware and software mechanisms and high throughput processors. Due to onboard storage restrictions and telemetry downlink limitations these systems must pre-process and reduce the data before sending it to the ground. This onboard processing and realtime requirement load may mean that newer more powerful processors are needed even though acceptable radiation-hardened versions have not yet been released. CALIPSO's single board computer payload controller processor is actually a set of four (4) voting non-radiation hardened COTS Power PC 603r's built on a single width VME card by General Dynamics Advanced Information Systems (GDAIS). Significant radiation concerns for CALIPSO and other Low Earth Orbit (LEO) satellites include the South Atlantic Anomaly (SAA), the north and south poles and strong solar events. Over much of South America and extending into the South Atlantic Ocean the Van Allen radiation belts dip to just 200-800km and spacecraft entering this area are subjected to high energy protons and experience higher than normal Single Event Upset (SEU) and Single Event Latch-up (SEL) rates. Although less significant, spacecraft flying in the area around the poles experience similar upsets. Finally, powerful solar proton events in the range of 10MeV/10pfu to 100MeV/1pfu as are forecasted and tracked by NOAA's Space Environment Center in Colorado can result in Single Event Upset (SEU), Single Event Latch-up (SEL) and permanent failures such as Single Event Gate Rupture (SEGR) in some technologies. (Galactic Cosmic Rays (GCRs) are another source, especially for gate rupture) CALIPSO mitigates common radiation concerns in its data handling through the use of redundant processors, radiation-hardened Application Specific Integrated Circuits (ASIC), hardware-based Error Detection and Correction (EDAC), processor and memory scrubbing, redundant boot code and mirrored files. After presenting a system overview this paper will expand on each of these strategies. Where applicable, related on-orbit data collected since the CALIPSO initial boot on May 4, 2006 will be noted.

Decoursey, Robert J.

Using Classical Reliability Models and Single Event Upset (SEU) Data to Determine Optimum Implementation Schemes for Triple Modular Redundancy (TMR) in SRAM-Based Field Programmable Gate Array (FPGA) Devices

Space applications are complex systems that require intricate trade analyses for optimum implementations. We focus on a subset of the trade process, using classical reliability theory and SEU data, to illustrate appropriate TMR scheme selection.

Field Programmable Gate Array (FPGA)

The Single Event Upset (SEU) response to 590 MeV protons

The presence of high-energy protons in cosmic rays, solar flares, and trapped radiation belts around Jupiter poses a threat to the Galileo project. Results of a test of 10 device types (including 1K RAM, 4-bit microP sequencer, 4-bit slice, 9-bit data register, 4-bit shift register, octal flip-flop, and 4-bit counter) exposed to 590 MeV protons at the Swiss Institute of Nuclear Research are presented to clarify the picture of SEU response to the high-energy proton environment of Jupiter. It is concluded that the data obtained should remove the concern that nuclear reaction products generated by protons external to the device can cause significant alteration in the device SEU response. The data also show only modest increases in SEU cross section as proton energies are increased up to the upper limits of energy for both the terrestrial and Jovian trapped proton belts.

Nichols, D. K.

Experimental evidence for a new single-event upset (SEU) mode in a CMOS SRAM obtained from model verification

Modeling of SEU has been done in a CMOS static RAM containing 1-micron-channel-length transistors fabricated from a p-well epilayer process using both circuit-simulation and numerical-simulation techniques. The modeling results have been experimentally verified with the aid of heavy-ion beams obtained from a three-stage tandem van de Graaff accelerator. Experimental evidence for a novel SEU mode in an ON n-channel device is presented.

Zoutendyk, J. A.

Single-event upset (SEU) in a DRAM with on-chip error correction

Results are given of SEU measurements on 256K dynamic RAMs with on-chip error correction. They are claimed to be the first ever reported. A (12/8) Hamming error-correcting code was incorporated in the layout. Physical separation of the bits in each code word was used to guard against multiple bits being disrupted in any given word. Significant reduction in observed errors is reported.

Zoutendyk, J. A.

Single event upset (SEU) testing at JPL

It is believed that the increase in SEUs with more modern devices may have serious consequences for future space missions. The physics behind an SEU is discussed as well as SEU test philosophy and equipment, and testing results. It is concluded that the problem may be ameliorated by careful device selection and the use of redundancy or error correction.

Coss, James R.

Investigation of single-event upset (SEU) in an advanced bipolar process

An extensive analytical and experimental study SEU in an advanced silicon bipolar process was made. The modeling used process and device parameters to model the SEU charge, collection, and circuit response derived from a special version of PISCES in cylindrical coordinates and SPICE, respectively. Data are reported for test cells of various sizes.

Zoutendyk, John A.

Single Event Effects Test Results for the Actel ProASIC Plus and Altera Stratix-II Field Programmable Gate Arrays

This work describes radiation testing of Actel's ProASIC Plus and Altera's Stratix-II FPGAs. The Actel Device Under Test (DUT) was a ProASIC Plus APA300-PQ208 nonvolatile, field reprogrammable device which is based on a 0.22micron flash-based LVCMOS technology. Limited investigation has taken place into flash based FPGA technologies, therefore this test served as a preliminary reference point for various SEE behaviors. The Altera DUT was a Stratix-II EP2S60F1020C4. Single Event Upset (SEU) and Single Event Latchup (SEL) were the focus of these studies. For the Actel, a latchup test was done at an effective LET of 75.0 MeV-sq cm/mg at room temperature, and no latchup was detected when irradiated to a total fluence of 1 x 10(exp 7) particles/sq cm. The Altera part was shown to latchup at room temperature.

heavy ions