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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Ion Exchange Gels Allow Organic Electrochemical Transistor Operation with Hydrophobic Polymers in Aqueous Solution

Conjugated-polymer-based organic electrochemical transistors (OECTs) are being studied for applications ranging from biochemical sensing to neural interfaces. While new polymers that interface digital electronics with the aqueous chemistry of life are being developed, the majority of high-performance organic transistor materials are poor at transporting biologically relevant ions. Here, the operating mode of an organic transistor is changed from that of an electrolyte-gated organic field-effect transistor (EGOFET) to that of an OECT by incorporating an ion exchange gel between the active layer and the aqueous electrolyte. This device works by taking up biologically relevant ions from solution and injecting more hydrophobic ions into the active layer. Using poly[2,5-bis(3-tetradecylthiophen-2-yl) thieno[3,2-b]thiophene] as the active layer and a blend of an ionic liquid, 1-butyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide, and poly(vinylidene fluoride-co-hexafluoropropylene) as the ion exchange gel, four orders of magnitude improvement in device transconductance and a 100-fold increase in kinetics are demonstrated. The ability of the ion-exchange-gel OECT to record biological signals by measuring the action potentials of a Venus flytrap is demonstrated. These results show the possibility of using interface engineering to open up a wider palette of organic semiconductors as OECTs that can be gated by aqueous solutions.

Bischak, Connor G.↗
DOE OSTI2020

Soft x-ray absorption spectroscopy and magnetic circular dichroism as operando probes of complex oxide electrolyte gate transistors

Electrolyte-based transistors utilizing ionic liquids/gels have been highly successful in the study of charge-density-controlled phenomena, particularly in oxides. Experimental probes beyond transport have played a significant role, despite challenges in their application in electric double-layer transistors. Here, we demonstrate the application of synchrotron soft x-ray absorption spectroscopy (XAS) and x-ray magnetic circular dichroism (XMCD) as operando probes of the charge state and magnetism in ion-gel-gated ferromagnetic perovskite films. Electrochemical response via oxygen vacancies at positive gate bias in LaAlO 3 (001)/La 0.5 Sr 0.5 CoO 3-δ is used as a test case. XAS/XMCD measurements of 4–25 unit-cell-thick films first probe the evolution of hole doping (from the O K-edge pre-peak) and ferromagnetism (at the Co L-edges), to establish a baseline. Operando soft XAS/XMCD of electrolyte-gated films is then demonstrated, using optimized spin-coated gels with a thickness of ~1 μm and a specific composition. The application of gate voltages up to +4 V is shown to dramatically suppress the O K-edge XAS pre-peak intensity and Co L-edge XMCD, thus enabling the Co valence and ferromagnetism to be tracked upon gate-induced reduction. Soft XAS and XMCD, with appropriate electrolyte design, are thus established to be viable for the operando characterization of electrolyte-gated oxides.

Yu, Biqiong↗
DOE OSTI2019

Low-Voltage, CMOS-Free Synaptic Memory Based on Li X TiO 2 Redox Transistors

Neuromorphic computers based on analogue neural networks aim to substantially lower computing power by reducing the need to shuttle data between memory and logic units. Artificial synapses containing nonvolatile analogue conductance states enable direct computation using memory elements; however, most nonvolatile analogue memories require high write voltages and large current densities and are accompanied by nonlinear and unpredictable weight updates. Here, we develop an inorganic redox transistor based on electrochemical lithium-ion insertion into Li X TiO 2 that displays linear weight updates at both low current densities and low write voltages. The write voltage, as low as 200 mV at room temperature, is achieved by minimizing the open-circuit voltage and using a low-voltage diffusive memristor selector. We further show that the Li X TiO 2 redox transistor can achieve an extremely sharp transistor subthreshold slope of just 40 mV/decade when operating in an electrochemically driven phase transformation regime.

42 ENGINEERING↗
DOE OSTI2023

AlGaN High Electron Mobility Transistor for High-Temperature Logic

Here we report on AlGaN high electron mobility transistor (HEMT)-based logic development, using combined enhancement- and depletion-mode transistors to fabricate inverters with operation from room temperature up to 500°C. Our development approach included: (a) characterizing temperature-dependent carrier transport for different AlGaN HEMT heterostructures, (b) developing a suitable gate metal scheme for use in high temperatures, and (c) over-temperature testing of discrete devices and inverters. Hall mobility data (from 30°C to 500°C) revealed the reference GaN-channel HEMT experienced a 6.9x reduction in mobility, whereas the AlGaN channel HEMTs experienced about a 3.1x reduction. Furthermore, a greater aluminum contrast between the barrier and channel enabled higher carrier densities in the two-dimensional electron gas for all temperatures. The combination of reduced variation in mobility with temperature and high sheet carrier concentration showed that an Al-rich AlGaN-channel HEMT with a high barrier-to-channel aluminum contrast is the best option for an extreme temperature HEMT design. Three gate metal stacks were selected for low resistivity, high melting point, low thermal expansion coefficient, and high expected barrier height. The impact of thermal cycling was examined through electrical characterization of samples measured before and after rapid thermal anneal. The 200-nm tungsten gate metallization was the top performer with minimal reduction in drain current, a slightly positive threshold voltage shift, and about an order of magnitude advantage over the other gates in on-to-off current ratio. After incorporating the tungsten gate metal stack in device fabrication, characterization of transistors and inverters from room temperature up to 500°C was performed. The enhancement-mode (e-mode) devices’ resistance started increasing at about 200°C, resulting in drain current degradation. This phenomenon was not observed in depletion-mode (d-mode) devices but highlights a challenge for inverters in an e-mode driver and d-mode load configuration.

42 ENGINEERING↗
DOE OSTI2020

Thermal Assessment and In-Situ Monitoring of Insulated Gate Bipolar Transistors in Power Electronic Modules: Preprint

Insulated gate bipolar transistor (IGBT) power modules are devices commonly used for switching of high voltages and currents. Usage and environmental conditions can cause these power modules to degrade over time, and this gradual process may eventually lead to catastrophic failure of the device. This degradation process may cause some early performance symptoms related to the state of health of the power module, making it possible to detect reliability degradation of the IGBT module. Testing can be used to accelerate this process, permitting a rapid determination of whether specific declines in device reliability can be characterized. In this study, thermal cycling was conducted on multiple power modules simultaneously in order to assess the effect of thermal cycling on the degradation of the power module. In-situ monitoring of temperature was performed from inside each power module using high temperature thermocouples. Device imaging and characterization was performed along with temperature data analysis, to assess failure modes and mechanisms within the power modules. While the experiment was aimed to assess the potential damage effects of thermal cycling on die attach, results indicated that wirebond degradation was the life limiting failure mechanism.

33 ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2019

Photo‐/Thermal‐Responsive Field‐Effect Transistor upon Blending Polymeric Semiconductor with Hexaarylbiimidazole toward Photonically Programmable and Thermally Erasable Memory Device

Abstract It is shown that the semiconducting performance of field‐effect transistors (FETs) with PDPP4T (poly(diketopyrrolopyrrole‐quaterthiophene)) can be reversibly tuned by UV light irradiation and thermal heating after blending with the photochromic hexaarylbiimidazole compound ( p ‐NO 2 ‐HABI). A photo‐/thermal‐responsive FET with a blend thin film of PDPP4T and p ‐NO 2 ‐HABI is successfully fabricated. The transfer characteristics are altered significantly with current enhanced up to 10 6 ‐fold at V G = 0 V after UV light irradiation. However, further heating results in the recovery of the transfer curve. This approach can be extended to other semiconducting polymers such as P3HT (poly(3‐hexyl thiophene)), PBTTT (poly(2,5‐bis(3‐tetradecylthiophen‐2‐yl)thieno[3,2‐b] thiophene)) and PDPPDTT (poly(diketopyrrolopyrrole‐dithienothiophene)). It is hypothesized that TPIRs (2,4,5‐triphenylimidazolyl radicals) formed from p ‐NO 2 ‐HABI after UV light irradiation can interact with charge defects at the gate dielectric–semiconductor interface and those in the semiconducting layer to induce more hole carriers in the semiconducting channel. The application of the blend thin film of PDPP4T and p ‐NO 2 ‐HABI is further demonstrated to fabricate the photonically programmable and thermally erasable FET‐based nonvolatile memory devices that are advantageous in terms of i) high ON/OFF current ratio, ii) nondestructive reading at low electrical bias, and iii) reasonably highly stable ON‐state and OFF‐state.

Liu, Yidong↗
DOE OSTI2025

Impact of 12-nm FinFET Technology Variations on TID Effects: A Comparative Study of GF 12LP and 12LP+ at the Transistor Level

Here, this article presents a comparative analysis of total ionizing dose (TID) response in GlobalFoundries’ (GF) 12 low-power (LP) and 12LP+12-nm bulk fin field effect transistor (FinFET) technologies using 10-keV X-rays. Our findings show that 12LP+ n-type transistors demonstrate higher sensitivity to TID degradation of the off-state leakage drain current compared to 12LP. Data indicate that for both 12LP and 12LP+, transistors with higher threshold voltages (VTs) exhibit lower off-state drain-source leakage postirradiation compared to transistors with lower VTs. Data consistently show that transistors with fewer fins per transistor show superior TID tolerance, in both 12LP and 12LP+ technologies. Lower VT transistors in both technologies display similar preirradiation leakage currents. On the other hand, higher VT transistors in 12LP+ show lower preirradiation leakage currents than those in 12LP, highlighting that the front-end-of-line of 12LP+ technology has been modified compared to 12LP. p-type devices in 12LP+ presented negligible degradation. Larger TID sensitivity in 12LP+ might be attributed to the implementation of dual-metal gate work functions, reduced halo doping, deeper source/drain (S/D) doping profiles, and/or 12LP+ having narrower fins compared to 12LP.

Dual-metal gate work functions↗
DOE OSTI2026

Efficient and Robust p-Type Transistor Based on Ultrawide-Bandgap Semiconductor

The p-type transistor is an indispensable component of semiconductor technology, enabling a complementary operation with n-channel transistors for computation, storage, and communication. Achieving both high robustness and high efficiency is highly desirable but challenging for p-type transistors due to the limited semiconductors with reliable hole transport and their high activation energies. Here, in this study, we achieved a robust yet efficient p-type transistor by heterogeneously integrating an ultrawide-bandgap semiconductor and a high-κ dielectric layer through van der Waals integration. The p-type transistor employs a two-dimensional hole channel on hydrogenated diamond (bandgap 5.6 eV) combined with a high-κ (30.5) SrTiO 3 perovskite membrane. At room temperature, the transistor exhibits stable operation with a high on-current (∼200 mA/mm), low subthreshold swing (70 mV/dec), high hole mobility (566 cm 2 /(V·s) to 572 cm 2 /(V·s)), and high on–off ratio (∼10 9 ). Furthermore, tuning the annealing temperature allows operation in either enhancement or depletion mode. The robust p-type transistor with high efficiency holds great potential for future power electronics, ultraviolet (UV) optoelectronics, and harsh-environment electronic applications.

high-κ membrane↗
DOE OSTI2024

Reducing the Barrier Height in Organic Transistors

Abstract Reducing the Schottky barrier height and Fermi level de‐pinning in metal‐organic semiconductor contacts are crucial for enhancing the performance of organic transistors. The reduction of the Schottky barrier height in bottom‐contact top‐gate organic transistors is demonstrated by adding 1 nm thick atomic layer deposited Al 2 O 3 on the source and drain contacts. By using two different donor‐acceptor copolymers, both p‐ and n‐ type transistors are investigated. Temperature‐dependent current–voltage measurements from non‐treated, self‐assembled monolayer treated, and Al 2 O 3 treated Au source‐drain contact field‐effect transistors with varying channel lengths are carried out. The drain current versus drain voltage near zero gate voltage, which may be described by the thermionic emission model at temperatures above 150 K, allows the estimation of the Schottky barrier height ( φ B ). The Al 2 O 3 contact‐treated transistors show more than 40% lower φ B compared with the non‐treated contacts in the p ‐type transistor. Similarly, an isoindigo‐based transistor, with n ‐type transport, shows a reduction in φ B with Al 2 O 3 treated contacts suggesting that such ultrathin oxide layers provide a universal method for reducing the barrier height.

Ghobadi, Arash↗
DOE OSTI2023

High voltage switch with cascaded transistor topology

A switching apparatus includes three or more series-connected transistors, and it further includes a balancing network. The balancing network includes a resistor network configured to divide a voltage from a voltage source across the series-connected transistors. The resistor network includes at least two resistive legs connected in parallel. In each resistive leg, two or more resistors are connected in series. The balancing network may further comprise at least one capacitive leg of series-connected capacitors connected across the series-connected transistors, and it may further comprise at least one leg of series-connected avalanche diodes connected across the series-connected transistors for overvoltage protection. In example embodiments, the series-connected transistors are JFETs. In other example embodiments, the series-connected transistors may be HEMTs or GaN transistors.

Gill, Lee↗
DOE OSTI2019

Studying the Characteristics of Transistors Based on Gallium Nitride Heterostructures Grown by Ammonia Molecular Beam Epitaxy on Sapphire and Silicon Substrates

Abstracts: Ammonia molecular-beam epitaxy has been used to grow gallium nitride (GaN) transistor heterostructures on sapphire and silicon substrates. GaN transistors with a 1.2-mm periphery fabricated on substrates of both types exhibited similar high static characteristics: saturation current density above 0.75 A/mm, transconductance above 300 mS/mm, and breakdown voltage above 120 V. Measurements of the small-signal parameters showed that transistors based on silicon substrates possessed high gain in a frequency range up to 5 GHz; the specific output power at 1 GHz amounted to 5 W/mm for transistors on sapphire substrate and 2 W/mm for transistors on silicon substrate.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2026

Gate-All-Around Nanowire Field-Effect Transistors: A Historical Perspective

The development of transistor architectures, evolving from 2D planar metal-oxide-semiconductor field-effect transistors (MOSFETs) to FinFETs and then to gate-all-around nanowire (GAANW) FETs, plays a crucial role in downscaling technology nodes in the semiconductor industry. This perspective reviews the concept of MOSFETs and summarizes this historical development with particular emphasis on GAANW transistors due to their importance in next-generation technology for nodes below 3 nm. Specifically, the concept of GAANW transistors and their advantages over planar and FinFET devices for further scaling are presented, along with a discussion of their transition from early conceptual ideas to laboratory demonstrations and, ultimately, industrial adoption. Furthermore, potential solutions, such as complementary FETs (CFETs) and 2D semiconductor-based FETs, and their associated challenges for the future generation, known as the Angstrom Era, are discussed in a technological roadmap. In conclusion, this perspective may inspire both industry and academia in future research directions for realizing the Angstrom Era.

gate-all-around transistors↗
DOE OSTI2019

Gate Quantum Capacitance Effects in Nanoscale Transistors

As the physical dimensions of a transistor gate continue to shrink to a few atoms, performance can be increasingly determined by the limited electronic density of states (DOS) in the gate and the gate quantum capacitance (C Q ). We demonstrate the impact of gate C Q and the dimensionality of the gate electrode on the performance of nanoscale transistors through analytical electrostatics modeling. For low-dimensional gates, the gate charge can limit the channel charge, and the transfer characteristics of the device become dependent on the gate DOS. Here, we experimentally observe for the first time, room-temperature gate quantization features in the transfer characteristics of single-walled carbon nanotube (CNT)-gated ultrathin silicon-on-insulator (SOI) channel transistors; features which can be attributed to the Van Hove singularities in the one-dimensional DOS of the CNT gate. In addition to being an important aspect of future transistor design, potential applications of this phenomenon include multilevel transistors with suitable transfer characteristics obtained via engineered gate DOS.

77 NANOSCIENCE AND NANOTECHNOLOGY↗