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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Wafer-based charged particle accelerator, wafer components, methods, and applications

A wafer-based charged particle accelerator includes a charged particle source and at least one RF charged particle accelerator wafer sub-assembly and a power supply coupled to the at least one RF charged particle accelerator wafer sub-assembly. The wafer-based charged particle accelerator may further include a beam current-sensor. The wafer-based charged particle accelerator may further include at least a second RF charged particle accelerator wafer sub-assembly and at least one ESQ charged particle focusing wafer. Fabrication methods are disclosed for RF charged particle accelerator wafer sub-assemblies, ESQ charged particle focusing wafers, and the wafer-based charged particle accelerator.

Lal, Amit↗
DOE OSTI2020

Low Cost (CAPEX and variable): Tool design for cell and module fabrication with thin, free-standing silicon wafers

This project aimed to develop technologies that can potentially enable free-standing thin (<80 μm) wafer in today’s manufacturing lines with high production yield, and thereby reduce capex barriers of silicon photovoltaics cells and modules. One of the major benefits is that thin wafer dramatically reduces the amount of polysilicon required. As a result, it can lead to reduction in the capital expenditures associated with polysilicon refining and wafer fabrication, which together are more than half of the total capital expenditure to manufacture Si PV module. We focused our efforts on developing the tools needed to enable high yield fabrication of wafer, cell, and module with thin silicon wafers. However, as the wafer thickness reduces, the major challenge is that wafer breakage increases significantly. Three technological areas were explored in this project to improve the production yield of the silicon wafer, namely detection of edge cracks via dark-field near-infrared (NIR) scattering; (2) wafer handling using controlled temperature profiles; (3) manufacturable low-stress cell interconnection for multiwire. First, the formation of wafer cracks in submillimeter length is one of the reasons that causes wafer breakages. Crack detection tools are needed to enable us to locate and track the wafer crack during manufacturing, so that we can improve the process to reduce initialization. The state-of-the-art crack detection technique cannot fulfill the need for measuring submillimeter edge cracks detrimental for thin wafers. The prototype developed in this project demonstrates the scanning of microcracks near wafer edges. With a semi-automatic laboratory setup, the submillimeter cracks were reliably detected near the edges in multi-Si wafers. The smallest detectable crack is 200 µm in length in slow scans; and submillimeter cracks are detected in high-throughput scans at the scan speed of >0.5 m/s, which is compatible with the inline detection of a manufacturing line at least 1 sec/wafer. This detection limit is a significant advancement in comparison to the benchmarked industrial tool. Second, wafer handling with the well-controlled temperature profile was thought to be the solution to reduce crack initiation and propagation during the manufacturing. However, without crack detection being widely adopted in production line, we did not find a strong industrial pull toward this technology. We did an initial literature survey and then diverted our efforts to the other tasks. Third, the innovation on low-stress multi-wire interconnection tackles a fundamental problem in the standard interconnection scheme. The standard over-under “zig-zag” interconnection induces a significant amount of stress into the soldering point on the cell whenever PV module is under stress, e.g., thermal cycling, transportation, and installation. Therefore, the interconnection process was re-designed in this project to allow for significant movement between adjacent solar cells, e.g., due to thermal expansion, without building up stresses on the solar cells or solder joints. The new interconnection method with the cross-connect wire also simplifies the tabbing and stringing process by replacing the standard over-under method with an off-cell interconnect from top to bottom. A manual tabbing and stringing tool for this new process was prototyped in the lab to demonstrate the fabrication of this new interconnection design. During the test with brass sheets as our “testing cells”, it was found that the mechanical cycling test only broke the interconnection after more than 50,000 cycles, which is equivalent to more than 130 years of the day-and-night thermal cycles. Lastly, throughout the project, we continuously analyzed the PV market with techno-economic analysis to identify the opportunity for thin Si adoption. Even though the drastic cost reduction has already happened in the past five years, our analysis results indicated that we can still save quite significantly in both manufacturing cost and factory capex, Particularly, in order to grow the PV manufacturing capacity to multi-terawatt level, reducing the thickness of silicon wafer is one of the most effective ways to quickly reduce factory capex, and sustain the high growth rate. The technologies developed in this project are readily available to provide some assistances in tackling the production yield problem.

14 SOLAR ENERGY↗
DOE OSTI2024

Passivated Contacts for Direct Wafer Product (Final Technical Report)

This TCF project developed a thin-oxide (SiO 2 )/polycrystalline silicon (poly-Si) passivated contact solar cell on CubicPV's (formally 1366 Technologies, Inc.) Direct Wafer® Product (DWP) kerfless wafers. The project used two NREL-developed technologies described in U.S. Patent No. 9,911,873, Hydrogenation of Passivated Contacts and U.S. Patent Application Serial No. 15/890,172, Doped Passivated Contacts . The project was motivated by a potential higher efficiency cell (compared to a PERC cell) using passivated contacts on the ultra-low cost kerfless wafers grown using the Direct Wafer process. The hope was to accelerate market adoption of the cell and wafer by delivering the lowest LCOE in the PV industry. The project tested both n-type and p-type SiO 2 /poly-Si passivated contacts grown by thermal oxidation and plasma enhanced chemical vapor deposition (PECVD) of the poly-Si layer on DWP with varying wafer resistivities. Both deposition techniques are industry standards and thus economically viable methods for commercializing the contacts. The results indicated that both n-type and p-type poly-Si passivated contacts can be formed on polycrystalline DWP wafers, but implied open-circuit voltages (i Voc ) were limited to below 0.65 mV (compared with ~ 730 mV on n-Cz wafers). Diffusion of H to the Si/SiO 2 /poly-Si interface was key to obtaining high i Voc values. In this study, H was diffused from a high-temperature SiN x layer deposited over the poly-Si layer during a high-temperature firing step, similar to one used for screen printed metals. The study concluded that poly-Si passivated contacts on DWP wafers passivated the surface of the wafers as well as PERC passivated surfaces, which use a less expensive dielectric layer stack. The project showed that Direct Wafer Product wafers grown by CubicPV could produce high i Voc values (~0.647 mV), which could produce a cell over 20% efficient with proper processing and metallization. These cells, though not economically viable in 2024 as a stand-alone cell, could be integrated with a wide-bandgap top solar cell to form a two-junction tandem cell that could be viable under certain circumstances. This is because the bottom cell of a 30%, two-terminal tandem only needs to be a 20% cell under one-sun conditions. Thus, the DWP could be an ideal low-cost wafer for tandems. The project also revealed that a TOPCon type cell could be formed on a p-type DWP wafer using a P-diffused emitter and a p-type poly-Si contact. In fact, the p-type version of the poly-Si contact out-performed the n-type version for a variety of wafer resistivities, from highly doped to lowly doped. This curiosity requires more work to understand because on Cz wafers, the n-type poly-Si contact is of much higher quality than the p-type version.

14 SOLAR ENERGY↗
DOE OSTI2020

Technoeconomic Analysis of Photovoltaics Module Manufacturing with Thin Silicon Wafers

Reducing silicon usage by adopting thinner wafers can significantly reduce capital expenditure (capex) and cost, and thus accelerate the growth of manufacturing capacity and deployment. In this work, we evaluated potential benefits of thin Si wafers for current and future PV modules. We apply a technoeconomic framework that couples bottom-up cost model, and a cash-flow growth model to analyze PV modules with thin wafers. First, we show that, comparing the current PERC with 160 um thick wafers to the high-efficiency concept with 50 um thin wafers, the capex is reduced from 0.39 to 0.2 $/(W/year) while the cost is from 0.32 to 0.2 $/W. Second, the potential of accelerated deployment is analyzed for the highefficiency thin wafer concept. We found the significant advantages of higher growth rate (~20% relative) and higher deployment plateau (~3 times) than the current PERC modules. modules with thin wafers. First, we show that, comparing the current PERC with 160 um thick wafers to the high-efficiency concept with 50 um thin wafers, the capex is reduced from 0.39 to 0.2 $/(W/year) while the cost is from 0.32 to 0.2 $/W. Second, the potential of accelerated deployment is analyzed for the highefficiency thin wafer concept. We found the significant advantages of higher growth rate (~20% relative) and higher deployment plateau (~3 times) than the current PERC modules.

14 SOLAR ENERGY↗
DOE OSTI2021

System and method for shingling wafer strips connected in parallel

A solar device includes a first string of first solar wafers, wherein a plurality of the first solar wafers each overlap with at least one vertically adjacent solar wafer from the first string. Additionally, the solar device includes a second string of second solar wafers, wherein a plurality of the second solar wafers each overlap with at least one vertically adjacent solar wafer from the second string, wherein a plurality of the first solar wafers overlap with one or more of the plurality of second solar wafers to electrically connect horizontally adjacent solar wafers in parallel.

Caswell, Nathaniel Alexis↗
DOE OSTI2023

System and method for shingling wafer strips connected in parallel

A solar device includes a first string of first solar wafers, wherein a plurality of the first solar wafers each overlap with at least one vertically adjacent solar wafer from the first string. Additionally, the solar device includes a second string of second solar wafers, wherein a plurality of the second solar wafers each overlap with at least one vertically adjacent solar wafer from the second string, wherein a plurality of the first solar wafers overlap with one or more of the plurality of second solar wafers to electrically connect horizontally adjacent solar wafers in parallel.

Caswell, Nathaniel↗
DOE OSTI2021

On the in-plane vibrations and electromechanical resonance characteristics of non-uniformly polarized rectangular piezoelectric wafers: Selective mode-type excitation and specific mode enhancement

Here, we investigate the in-plane vibrations and electromechanical resonance characteristics of non-uniformly polarized rectangular piezoelectric wafers. Non-uniform polarization is represented as a non-uniform electromechanical coupling coefficient using a polarization function. Governing equations are derived for the forced in-plane vibrations of a thin wafer under the assumption of generalized plane stress. The effect of non-uniform polarization is explicitly obtained in the forcing terms of the governing equations. These equations are then recast into a variational weak form that is then solved using the finite element method to obtain the displacement fields for different modes. The electromechanical response of a non-uniformly polarized piezoelectric wafer is derived in terms of the out-of-plane displacement profile on the surface of the wafer. Using the derived analytical expression, a necessary and sufficient condition for the presence/absence of a vibrational mode in the electromechanical impedance spectrum is obtained. Based on this condition, criteria for selective mode-type excitation and specific mode enhancement of vibrational modes in the electromechanical impedance spectrum are postulated. Selective mode-type excitation of in-plane extensional and shear modes is demonstrated for a square wafer and that of in-plane bending modes is demonstrated for a rectangular wafer. Specific mode enhancement is demonstrated for both square and rectangular wafers. In addition, it is also demonstrated how the criteria can be used to suppress specific vibrational modes in the electromechanical impedance spectrum. The proposed methodology of using non-uniformly polarized piezoelectric wafers finds application in the design of single element transducers with multi-frequency operation, frequency-tuned receivers/sensors, acoustic holograms, designing acoustic beams of prescribed shape/lobes, and other non-traditional applications such as information storage.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Using machine learning with optical profilometry for GaN wafer screening

Abstract To improve the manufacturing process of GaN wafers, inexpensive wafer screening techniques are required to both provide feedback to the manufacturing process and prevent fabrication on low quality or defective wafers, thus reducing costs resulting from wasted processing effort. Many of the wafer scale characterization techniques—including optical profilometry—produce difficult to interpret results, while models using classical programming techniques require laborious translation of the human-generated data interpretation methodology. Alternatively, machine learning techniques are effective at producing such models if sufficient data is available. For this research project, we fabricated over 6000 vertical PiN GaN diodes across 10 wafers. Using low resolution wafer scale optical profilometry data taken before fabrication, we successfully trained four different machine learning models. All models predict device pass and fail with 70–75% accuracy, and the wafer yield can be predicted within 15% error on the majority of wafers.

36 MATERIALS SCIENCE↗
DOE OSTI2021

Wafer-level handle replacement

A wafer includes a number of die, with each die including electronic integrated circuits and optical devices. The wafer has a top surface and a bottom surface and a base layer. The bottom surface of the wafer corresponds to a bottom surface of the base layer. A wafer support system is attached to the top surface of the wafer. A thickness of the base layer is removed to expose a target layer within the wafer and to give the wafer a new bottom surface. A replacement handle structure is attached to the new bottom surface of the wafer. The replacement handle structure includes a first thickness region and a second thickness region. The first thickness region is positioned closest to the new bottom surface. The first thickness region is formed of an optical cladding material that mitigates optical coupling between optical devices within the die and the replacement handle structure.

Meade, Roy Edward↗
DOE OSTI2023

Controlled Growth of Single‐Crystal Graphene Wafers on Twin‐Boundary‐Free Cu(111) Substrates

Single-crystal graphene (SCG) wafers are needed to enable mass-electronics and optoelectronics owing to their excellent properties and compatibility with silicon-based technology. Controlled synthesis of high-quality SCG wafers can be done exploiting single-crystal Cu(111) substrates as epitaxial growth substrates recently. However, current Cu(111) films prepared by magnetron sputtering on single-crystal sapphire wafers still suffer from in-plane twin boundaries, which degrade the SCG chemical vapor deposition. Here, in this study, it is shown how to eliminate twin boundaries on Cu and achieve 4 in. Cu(111) wafers with ≈95% crystallinity. The introduction of a temperature gradient on Cu films with designed texture during annealing drives abnormal grain growth across the whole Cu wafer. In-plane twin boundaries are eliminated via migration of out-of-plane grain boundaries. SCG wafers grown on the resulting single-crystal Cu(111) substrates exhibit improved crystallinity with >97% aligned graphene domains. As-synthesized SCG wafers exhibit an average carrier mobility up to 7284 cm 2 V −1 s −1 at room temperature from 103 devices and a uniform sheet resistance with only 5% deviation in 4 in. region.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Specific resonance mode enhancement and suppression using non-uniform polarization of piezoelectric wafers: Theory and experiments

In this work, we present experimental demonstration of specific resonance mode enhancement and suppression in circular and rectangular piezoelectric wafers with engineered non-uniform polarization profiles. The polarization profiles are designed based on the electromechanical impedance response of non-uniformly polarized wafers as obtained from the theory. The circular wafers are fabricated with non-uniform polarization profiles that involve a central polarized region surrounded by an unpolarized region. The radius of the polarization zone is designed based on the condition for specific mode enhancement obtained from the electromechanical impedance response of non-uniformly polarized wafers. We actually show how the condition can not only be used to enhance but also to suppress electromechanical resonances. Two kinds of wafers are designed and fabricated to specifically suppress second and third radial modes respectively. Similarly, rectangular wafers are designed with two different kinds of non-uniform polarization profiles — the first of which enhances the second in-plane extensional mode in the impedance spectrum and the second polarization profile suppresses all the electromechanical resonances pertaining to the in-plane extensional modes and selectively excites only the in-plane bending modes. The proposed approach of using non-uniformly polarized wafers finds application in designing multi-frequency sensors/transducers, frequency-tuned receivers, acoustic beamforming, and other non-traditional applications such as information storage.

36 MATERIALS SCIENCE↗
DOE OSTI2021

Acoustic Wafer Defect Detection System

Researchers at Los Alamos have developed the Acoustic Wafer Defect Detection System, a technology that enables rapid diagnosis of critical defects during wafer production. This technology is capable of both efficient and accurate detection of defects in wafers, including defects that are undetectable through current optical techniques. The system identifies the wafer defects by exciting resonant vibrations in the wafers and by exciting “crack breathing” modes. These vibrations cause the crack to periodically open and close. Specific resonance characteristics, combined with acoustic signatures resulting from crack breathing, result in a technique that is highly sensitive to cracked wafers. There are minimal custom parts used to build the system, and it can be easily implemented in nearly any wafer production plant with minimal modifications. We are seeking a commercialization partner to license the technology or partner through a Cooperative Research and Development Agreement (CRADA) to develop into a usable product for commercial purposes.

42 ENGINEERING↗
DOE OSTI2022

Temperature and illumination dependence of silicon heterojunction solar cells with a wide range of wafer resistivities

Abstract Recently, the significant improvements in the surface and contact passivation of silicon (Si) solar cells as well as their bulk quality have shifted their operating point to higher injections. Hence, they are less dependent on wafer doping. This shift opens an opportunity of using high‐resistivity wafers for practical photovoltaic applications, introducing a promising approach to push the cell efficiency towards the intrinsic limit and to improve the module reliability by increasing the cell breakdown voltage. Therefore, insights into the performance of Si solar cells using high‐resistivity wafers at various operating temperatures are of significant interest. In this study, we investigate the temperature‐ and illumination‐dependent performance of Si heterojunction (SHJ) solar cells using a wide range of wafer resistivities (between 3 and 1000 Ω⋅cm). Although a reduction in the passivation quality of the passivating contacts is observed at elevated temperature, the impact on the temperature coefficient of the open‐circuit voltage (TC V oc )—the dominant contributor to the temperature coefficient (TC) of the cell efficiency—is very limited. Their TC V oc are still dominated by the temperature dependence of the effective intrinsic carrier concentration. Furthermore, we also find that the investigated cells are more sensitive to temperature variation at lower illumination intensities. It is noteworthy that the efficiency of the cells fabricated using high‐resistivity wafers is comparable to that of the reference cells at any given temperature, highlighting the potential of using high‐resistivity wafers for solar cells.

14 SOLAR ENERGY↗