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At least 19 records

A Low-Complexity Circuit for On-Sensor Concurrent A/D Conversion and Compression

A low-complexity circuit for on-sensor compression is presented. The proposed circuit achieves complexity savings by combining a single-slope analog-to-digital converter with a Golomb-Rice entropy encoder and by implementing a low-complexity adaptation rule. The adaptation rule monitors the output codewords and minimizes their length by incrementing or decrementing the value of the Golomb-Rice coding parameter k. Its hardware implementation is one order of magnitude lower than existing adaptive algorithms. The compression circuit has been fabricated using a 0.35 micrometers CMOS technology and occupies an area of 0.0918 mm2. Test measurements confirm the validity of the design

Leon-Salas, Walter D.↗

Robust neural classifier circuits using asynchronous design

Aerospace neural circuits must be adaptive, offer a practical size-performance ratio, and be environmentally robust. Our approach to building such circuits combines asynchronous design with a new fuzzy/neural classifier model. Asynchronous circuits offer many design advantages for neural hardware and our hybrid fuzzy/neural model, using mainly min and max operators, promises a low circuit complexity. The general approach is described and a description of a use of rule-induction to further reduce circuit complexity is described.

Hurdle, John F.↗

Techniques for control of long-term reliability of complex integrated circuits. I - Reliability assurance by test vehicle qualification.

Development of an alternate approach to the conventional methods of reliability assurance for large-scale integrated circuits. The product treated is a large-scale T squared L array designed for space applications. The concept used is that of qualification of product by evaluation of the basic processing used in fabricating the product, providing an insight into its potential reliability. Test vehicles are described which enable evaluation of device characteristics, surface condition, and various parameters of the two-level metallization system used. Evaluation of these test vehicles is performed on a lot qualification basis, with the lot consisting of one wafer. Assembled test vehicles are evaluated by high temperature stress at 300 C for short time durations. Stressing at these temperatures provides a rapid method of evaluation and permits a go/no go decision to be made on the wafer lot in a timely fashion.

Van Vonno, N. W.↗

Frequency discriminator/phase detector

Circuit provides dual function of frequency discriminator/phase detector which reduces frequency acquisition time without adding to circuit complexity. Both frequency discriminators, in evaluated frequency discriminator/phase detector circuits, are effective two decades above and below center frequency.

Crow, R. B.↗

Technical support for digital systems technology development. Task order 1: ISP contention analysis and control

Alternatives for realizing a packet-based network switch for use on a frequency division multiple access/time division multiplexed (FDMA/TDM) geostationary communication satellite were investigated. Each of the eight downlink beams supports eight directed dwells. The design needed to accommodate multicast packets with very low probability of loss due to contention. Three switch architectures were designed and analyzed. An output-queued, shared bus system yielded a functionally simple system, utilizing a first-in, first-out (FIFO) memory per downlink dwell, but at the expense of a large total memory requirement. A shared memory architecture offered the most efficiency in memory requirements, requiring about half the memory of the shared bus design. The processing requirement for the shared-memory system adds system complexity that may offset the benefits of the smaller memory. An alternative design using a shared memory buffer per downlink beam decreases circuit complexity through a distributed design, and requires at most 1000 packets of memory more than the completely shared memory design. Modifications to the basic packet switch designs were proposed to accommodate circuit-switched traffic, which must be served on a periodic basis with minimal delay. Methods for dynamically controlling the downlink dwell lengths were developed and analyzed. These methods adapt quickly to changing traffic demands, and do not add significant complexity or cost to the satellite and ground station designs. Methods for reducing the memory requirement by not requiring the satellite to store full packets were also proposed and analyzed. In addition, optimal packet and dwell lengths were computed as functions of memory size for the three switch architectures.

Stehle, Roy H.↗

Design, processing, and testing of LSI arrays for space station

Data for the beam-leaded silicon-on-sapphire (SOS) process using the TA5388 dual-complementary pair plus inverted circuit show the stability of the dc device characteristics through the complete beam-lead processing and packaging steps. A more complex circuit, the TA6567 - a silicon-gate, voltage-sense BL/CMOS/SOS 256-bit RAM, has also been made that was functionally perfect at wafer probe. Efforts to increase the yield of this circuit and to obtain electrically perfect packaged units are discussed.

Schneider, W. C.↗

Design methods for fault-tolerant finite state machines

VLSI electronic circuits are increasingly being used in space-borne applications where high levels of radiation may induce faults, known as single event upsets. In this paper we review the classical methods of designing fault tolerant digital systems, with an emphasis on those methods which are particularly suitable for VLSI-implementation of finite state machines. Four methods are presented and will be compared in terms of design complexity, circuit size, and estimated circuit delay.

Niranjan, Shailesh↗

High Electron Mobility Transistor Structures on Sapphire Substrates Using CMOS Compatible Processing Techniques

System-on-a-chip (SOC) processes are under intense development for high-speed, high frequency transceiver circuitry. As frequencies, data rates, and circuit complexity increases, the need for substrates that enable high-speed analog operation, low-power digital circuitry, and excellent isolation between devices becomes increasingly critical. SiGe/Si modulation doped field effect transistors (MODFETs) with high carrier mobilities are currently under development to meet the active RF device needs. However, as the substrate normally used is Si, the low-to-modest substrate resistivity causes large losses in the passive elements required for a complete high frequency circuit. These losses are projected to become increasingly troublesome as device frequencies progress to the Ku-band (12 - 18 GHz) and beyond. Sapphire is an excellent substrate for high frequency SOC designs because it supports excellent both active and passive RF device performance, as well as low-power digital operations. We are developing high electron mobility SiGe/Si transistor structures on r-plane sapphire, using either in-situ grown n-MODFET structures or ion-implanted high electron mobility transistor (HEMT) structures. Advantages of the MODFET structures include high electron mobilities at all temperatures (relative to ion-implanted HEMT structures), with mobility continuously improving to cryogenic temperatures. We have measured electron mobilities over 1,200 and 13,000 sq cm/V-sec at room temperature and 0.25 K, respectively in MODFET structures. The electron carrier densities were 1.6 and 1.33 x 10(exp 12)/sq cm at room and liquid helium temperature, respectively, denoting excellent carrier confinement. Using this technique, we have observed electron mobilities as high as 900 sq cm/V-sec at room temperature at a carrier density of 1.3 x 10(exp 12)/sq cm. The temperature dependence of mobility for both the MODFET and HEMT structures provides insights into the mechanisms that allow for enhanced electron mobility as well as the processes that limit mobility, and will be presented.

Mueller, Carl↗

Yearlong 500 C Operational Demonstration of Up-Scaled 4H-SiC JFET Integrated Circuits

This work describes recent progress in the design, processing, and testing of significantly up-scaled 500 C durable 4H-SiC junction field effect transistor (JFET) integrated circuit (IC) technology with two-level interconnect undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for over one year at 500 C in air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500 C-durable circuit complexity from the 24 transistor ring oscillator ICs reported at HiTEC 2016. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for combustion engine sensing and control, planetary exploration, deep-well drilling monitoring, and other harsh-environment applications.

Silicon carbides↗

Microgravity Processing and Photonic Applications of Organic and Polymeric Materials

Some of the primary purposes of this work are to study important technologies, particularly involving thin films, relevant to organic and polymeric materials for improving applicability to optical circuitry and devices and to assess the contribution of convection on film quality in unit and microgravity environments. Among the most important materials processing techniques of interest in this work are solution-based and by physical vapor transport, both having proven gravitational and acceleration dependence. In particular, PolyDiAcetylenes (PDA's) and PhthaloCyanines (Pc's) are excellent NonLinear Optical (NLO) materials with the promise of significantly improved NLO properties through order and film quality enhancements possible through microgravity processing. Our approach is to focus research on integrated optical circuits and optoelectronic devices relevant to solution-based and vapor processes of interest in the Space Sciences Laboratory at the Marshall Space Flight Center (MSFC). Modification of organic materials is an important aspect of achieving more highly ordered structures in conjunction with microgravity processing. Parallel activities include characterization of materials for particular NLO properties and determination of appropriation device designs consistent with selected applications. One result of this work is the determination, theoretically, that buoyancy-driven convection occurs at low pressures in an ideal gas in a thermalgradient from source to sink. Subsequent experiment supports the theory. We have also determined theoretically that buoyancy-driven convection occurs during photodeposition of PDA, an MSFC-patented process for fabricating complex circuits, which is also supported by experiment. Finally, the discovery of intrinsic optical bistability in metal-free Pc films enables the possibility of the development of logic gate technology on the basis of these materials.

Frazier, Donald O.↗

An ingestible temperature-transmitter

Pill-sized transmitter measures deep body temperature in studies of circadian rhythm and indicates general health. Ingestible device is a compromise between accuracy, circuit complexity, size and transmission range.

Pope, J. M.↗

A high speed sequential decoder

The performance and theory of operation for the High Speed Hard Decision Sequential Decoder are delineated. The decoder is a forward error correction system which is capable of accepting data from binary-phase-shift-keyed and quadriphase-shift-keyed modems at input data rates up to 30 megabits per second. Test results show that the decoder is capable of maintaining a composite error rate of 0.00001 at an input E sub b/N sub o of 5.6 db. This performance has been obtained with minimum circuit complexity.

Lum, H., Jr.↗

Converter design techniques and applications

The design of transistorized voltage converters of the series, shunt, and switching types is developed and explained. The shunt converter has the smallest size, lowest weight, and lowest parts count. Regulation and stability are very good but efficiency is poor. The series converter is somewhat larger in size, heavier, uses more parts, and has an order of magnitude (10 to 1) decrease in regulation performance in comparison with the shunt converter. The switching converter tends to be a compromise with increased size, weight, and circuit complexity to gain in efficiency and regulation over a series converter. A switching converter will usually exhibit ringing in the output filter for some types of loads so it has only fair stability performance.-

Lalli, V. R.↗

Advanced space system concepts and their orbital support needs (1980 - 2000). Volume 2: Final report

The results are presented of a study which identifies over 100 new and highly capable space systems for the 1980-2000 time period: civilian systems which could bring benefits to large numbers of average citizens in everyday life, much enhance the kinds and levels of public services, increase the economic motivation for industrial investment in space, expand scientific horizons; and, in the military area, systems which could materially alter current concepts of tactical and strategic engagements. The requirements for space transportation, orbital support, and technology for these systems are derived, and those requirements likely to be shared between NASA and the DoD in the time period identified. The high leverage technologies for the time period are identified as very large microwave antennas and optics, high energy power subsystems, high precision and high power lasers, microelectronic circuit complexes and data processors, mosaic solid state sensing devices, and long-life cryogenic refrigerators.

Bekey, I.↗

A bandwidth-compressive modulation system

The phrase 'bandwidth-compressive modulation' means that the compression is achieved not by removing redundancy from the data (data compression), but rather by modulating the carrier phase and amplitude with blocks of data bits. The modulation described here is quadrature amplitude shift keying (QASK), a logical extension of quadrature phase shift keying, (QPSK, or quadriphase). QASK is a cost-effective form of combined phase-and-amplitude modulation. That is, n-bit QASK, like most phase-amplitude forms of modulation, requires considerably less transmitter power than comparably performing n-PSK, while among the class of all n-bit phase-modulation types, n-bit QASK performs nearly optimally but requires the least circuit complexity. A simple, unique microwave transmitter is described which provides high-rate QASK modulation with 4:1 bandwidth compression. A suppressed carrier multiple-loop QASK receiver provides the necessary phase tracking, automatic gain control (AGC), and symbol timing.

Smith, J. G.↗

Static inverter with synchronous output waveform synthesized by time-optimal-response feedback

Time-optimal-response 'bang-bang' or 'bang-hang' technique, using four feedback control loops, synthesizes static-inverter sinusoidal output waveform by self-oscillatory but yet synchronous pulse-frequency-modulation (SPFM). A single modular power stage per phase of ac output entails the minimum of circuit complexity while providing by feedback synthesis individual phase voltage regulation, phase position control and inherent compensation simultaneously for line and load disturbances. Clipped sinewave performance is described under off-limit load or input voltage conditions. Also, approaches to high power levels, 3-phase arraying and parallel modular connection are given.

Kernick, A.↗