Monolithic circuit test standards
Monolithic circuit test standards and methods for line certification
Adame, J. R.↗
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A semiautomatic test set for in-circuit testing of diodes.
In-circuit diodes testing by semiautomatic low current regulated voltage test set
Lutz, O. P.↗
Four-micron period ion-implanted bubble test circuits
Packaged magnetic bubble test circuits made with 4-micron period ion-implanted circuits were operated over -55 to +110 C. The circuits used bidirectional transfer and nondestructive detection and were made on bismuth-containing magnetic garnet films. Passivated circuits that incorporated an improved transfer conductor design were operated on films with higher Gilbert damping parameters. Potential advantages to using films with lower bubble aspect ratios for ion-implanted circuits are discussed. However nondestructive read-out detection was not realized with these 'flat' bubbles.
Nelson, T. J.↗
Assessing the SEU resistance of CMOS latches using alpha-particle sensitive test circuits
The importance of Cosmic Rays on the performance of integrated circuits (IC's) in a space environment is evident in the upset rate of the Tracking and Data Relay Satellite (TDRS) launched in Apr. 1983. This satellite experiences a single-event-upset (SEU) per day which must be corrected from the ground. Such experience caused a redesign of the Galileo spacecraft with SEU resistant IC's. The solution to the SEU problem continues to be important as the complexity of spacecraft grows, the feature size of IC's decreases, and as space systems are designed with circuits fabricated at non-radiation hardened foundries. This paper describes an approach for verifying the susceptibility of CMOS latches to heavy-ion induced state changes. The approach utilizes alpha particles to induce the upsets in test circuits. These test circuits are standard cells that have offset voltages which sensitize the circuits to upsets. These results are then used to calculate the upsetability at operating voltages. In this study results are presented for the alpha particle upset of a six-transistor static random access memory (SRAM) cell. Then a methodology is described for the analysis of a standard-cell inverter latch.
Buehler, M.↗
Method for characterizing the upset response of CMOS circuits using alpha-particle sensitive test circuits
A method for predicting the SEU susceptibility of a standard-cell D-latch using an alpha-particle sensitive SRAM, SPICE critical charge simulation results, and alpha-particle interaction physics. A technique utilizing test structures to quickly and inexpensively characterize the SEU sensitivity of standard cell latches intended for use in a space environment. This bench-level approach utilizes alpha particles to induce upsets in a low LET sensitive 4-k bit test SRAM. This SRAM consists of cells that employ an offset voltage to adjust their upset sensitivity and an enlarged sensitive drain junction to enhance the cell's upset rate.
Buehler, Martin G.↗
Universal nondestructive mm-wave integrated circuit test fixture
Monolithic microwave integrated circuit (MMIC) test includes a bias module having spring-loaded contacts which electrically engage pads on a chip carrier disposed in a recess of a base member. RF energy is applied to and passed from the chip carrier by chamfered edges of ridges in the waveguide passages of housings which are removably attached to the base member. Thru, Delay, and Short calibration standards having dimensions identical to those of the chip carrier assure accuracy and reliability of the test. The MMIC chip fits in an opening in the chip carrier with the boundaries of the MMIC lying on movable reference planes thereby establishing accuracy and flexibility.
Romanofsky, Robert R.↗
Traveling-Wave Tube Cold-Test Circuit Optimization Using CST MICROWAVE STUDIO
The internal optimizer of CST MICROWAVE STUDIO (MWS) was used along with an application-specific Visual Basic for Applications (VBA) script to develop a method to optimize traveling-wave tube (TWT) cold-test circuit performance. The optimization procedure allows simultaneous optimization of circuit specifications including on-axis interaction impedance, bandwidth or geometric limitations. The application of Microwave Studio to TWT cold-test circuit optimization is described.
Chevalier, Christine T.↗
Development and Analysis of Cold Trap for Use in Fission Surface Power-Primary Test Circuit
The design and analysis of a cold trap proposed for use in the purification of circulated eutectic sodium potassium (NaK-78) loops is presented. The cold trap is designed to be incorporated into the Fission Surface Power-Primary Test Circuit (FSP-PTC), which incorporates a pumped NaK loop to simulate in-space nuclear reactor-based technology using non-nuclear test methodology as developed by the Early Flight Fission-Test Facility. The FSP-PTC provides a test circuit for the development of fission surface power technology. This system operates at temperatures that would be similar to those found in a reactor (500-800 K). By dropping the operating temperature of a specified percentage of NaK flow through a bypass containing a forced circulation cold trap, the NaK purity level can be increased by precipitating oxides from the NaK and capturing them within the cold trap. This would prevent recirculation of these oxides back through the system, which may help prevent corrosion.
Wolfe, T. M.↗
Automatic integrated circuit test equipment.
Automatic high speed IC test equipment and procedure
AUTOMATIC CONTROL↗
Validation of monolithic circuit test standards through an integrated COS/MOS multiplexer Final report, 25 Jun. 1968 - 31 Dec. 1969
Validating test standards for process control and testing of integrated circuits
Feryszka, R.↗
Flip-flop resolving time test circuit
Integrated circuit (IC) flip-flop resolving time parameters are measured by wafer probing, without need of dicing or bonding, throught the incorporation of test structures on an IC together with the flip-flop to be measured. Several delays that are fabricated as part of the test circuit, including a voltage-controlled delay with a resolution of a few picosecs, are calibrated as part of the test procedure by integrating them into, and out of, the delay path of a ring oscillator. Each of the delay values is calculated by subtracting the period of the ring oscillator with the delay omitted from the period with the delay included. The delay measurement technique is sufficiently general for other applications. The technique is illustrated for the case of the flip-flop parameters of a 5-micron feature size NMOS circuit.
Rosenberger, F.↗
Submicrosecond Power-Switching Test Circuit
A circuit that changes an electrical load in a switching time shorter than 0.3 microsecond has been devised. This circuit can be used in testing the regulation characteristics of power-supply circuits . especially switching power-converter circuits that are supposed to be able to provide acceptably high degrees of regulation in response to rapid load transients. The combination of this power-switching circuit and a known passive constant load could be an attractive alternative to a typical commercially available load-bank circuit that can be made to operate in nominal constant-voltage, constant-current, and constant-resistance modes. The switching provided by a typical commercial load-bank circuit in the constant-resistance mode is not fast enough for testing of regulation in response to load transients. Moreover, some test engineers do not trust the test results obtained when using commercial load-bank circuits because the dynamic responses of those circuits are, variously, partly unknown and/or excessively complex. In contrast, the combination of this circuit and a passive constant load offers both rapid switching and known (or at least better known) load dynamics. The power-switching circuit (see figure) includes a signal-input section, a wide-hysteresis Schmitt trigger that prevents false triggering in the event of switch-contact bounce, a dual-bipolar-transistor power stage that drives the gate of a metal oxide semiconductor field-effect transistor (MOSFET), and the MOSFET, which is the output device that performs the switching of the load. The MOSFET in the specific version of the circuit shown in the figure is rated to stand off a potential of 100 V in the "off" state and to pass a current of 20 A in the "on" state. The switching time of this circuit (the characteristic time of rise or fall of the potential at the drain of the MOSFET) is .300 ns. The circuit can accept any of three control inputs . which one depending on the test that one seeks to perform: a repetitive waveform from a signal generator, momentary closure of a push-button switch, or closure or opening of a manually operated on/off switch. In the case of a signal generator, one can adjust the frequency and duty cycle as needed to obtain the desired AC power-supply response, which one could display on an oscilloscope. Momentary switch closure could be useful for obtaining (and, if desired, displaying on an oscilloscope set to trigger on an event) the response of a power supply to a single load transient. The on/off switch can be used to switch between load states in which static-load regulation measurements are performed.
Folk, Eric N.↗
Mark I Silicon Carbide Integrated Circuit Test Oven Assembly and Programming Guide
This report provides a parts list, with assembly and programming instructions for building firstgeneration (Mark I) compact test ovens; this oven design is customized for prolonged functional electrical testing of prototype silicon carbide (SiC) devices at temperatures up to 500 °C (932 °F). The general approach of using multiple compact ovens to perform long-term, high-temperature electronics testing efficiently is described in a conference paper (Izadnegahdar, Alain, et al.: Alternative Setup for LongDuration Low-Duty-Cycle 600 °C Ambient Testing of SiC Integrated Circuits. International Microelectronics Assembly and Packaging Society (iMAPS) HiTECH 2021 Technology Crossover Extravaganza, 2021), available at https://ntrs.nasa.gov/citations/20210011676. The new Mark I oven design described here offers several significant improvements over the compact oven described in that paper. For example, it is constructed from commercial off-the-shelf (COTS) components and requires minimal assembly. Much of the work involves drilling holes in the two aluminum project boxes, which contain the control electronics and the oven itself. The cost of components is less than $200 (USD) per oven, which makes constructing multiple ovens affordable. In addition, the two-box design separates the high-temperature heater from the electronics, which keeps the electronics cool, prolonging the lifetime of these components.
high temperature↗
Capabilities and Testing of the Fission Surface Power Primary Test Circuit (FSP-PTC)
An actively pumped alkali metal flow circuit, designed and fabricated at the NASA Marshall Space Flight Center, is currently undergoing testing in the Early Flight Fission Test Facility (EFF-TF). Sodium potassium (NaK), which was used in the SNAP-10A fission reactor, was selected as the primary coolant. Basic circuit components include: simulated reactor core, NaK to gas heat exchanger, electromagnetic (EM) liquid metal pump, liquid metal flowmeter, load/drain reservoir, expansion reservoir, test section, and instrumentation. Operation of the circuit is based around a 37-pin partial-array core (pin and flow path dimensions are the same as those in a full core), designed to operate at 33 kWt. NaK flow rates of greater than 1 kg/sec may be achieved, depending upon the power applied to the EM pump. The heat exchanger provides for the removal of thermal energy from the circuit, simulating the presence of an energy conversion system. The presence of the test section increases the versatility of the circuit. A second liquid metal pump, an energy conversion system, and highly instrumented thermal simulators are all being considered for inclusion within the test section. This paper summarizes the capabilities and ongoing testing of the Fission Surface Power Primary Test Circuit (FSP-PTC).
Garber, Anne E.↗
Documentation of Stainless Steel Lithium Circuit Test Section Design
The Early Flight Fission-Test Facilities (EFF-TF) team was tasked by Naval Reactors Prime Contract Team (NRPCT) to design, fabricate, and test an actively pumped lithium (Li) flow circuit. This Li circuit takes advantage of work in progress at the EFF TF on a stainless steel sodium/potassium (NaK) circuit. The effort involved modifying the original stainless steel NaK circuit such that it could be operated with Li in place of NaK. This new design considered freeze/thaw issues and required the addition of an expansion tank and expansion/extrusion volumes in the circuit plumbing. Instrumentation has been specified for Li and circuit heaters have been placed throughout the design to ensure adequate operational temperatures and no uncontrolled freezing of the Li. All major components have been designed and fabricated prior to circuit redesign for Li and were not modified. Basic circuit components include: reactor segment, Li to gas heat exchanger, electromagnetic liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and trace heaters. The reactor segment, based on a Los Alamos National Laboratory 100-kW design study with 120 fuel pins, is the only prototypic component in the circuit. However, due to earlier funding constraints, a 37-pin partial-array of the core, including the central three rings of fuel pins (pin and flow path dimensions are the same as those in the full design), was selected for fabrication and test. This Technical Publication summarizes the design and integration of the pumped liquid metal Li flow circuit as of May 1, 2005.
Godfroy, T. J.↗
Documentation of Stainless Steel Lithium Circuit Test Section Design
The Early Flight Fission-Test Facilities (EFF-TF) team was tasked by Naval Reactors Prime Contract Team (NRPCT) to design, fabricate, and test an actively pumped lithium (Li) flow circuit. This Li circuit takes advantage of work in progress at the EFF TF on a stainless steel sodium/potassium (NaK) circuit. The effort involved modifying the original stainless steel NaK circuit such that it could be operated with Li in place of NaK. This new design considered freeze/thaw issues and required the addition of an expansion tank and expansion/extrusion volumes in the circuit plumbing. Instrumentation has been specified for Li and circuit heaters have been placed throughout the design to ensure adequate operational temperatures and no uncontrolled freezing of the Li. All major components have been designed and fabricated prior to circuit redesign for Li and were not modified. Basic circuit components include: reactor segment, Li to gas heat exchanger, electromagnetic liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and trace heaters. The reactor segment, based on a Los Alamos National Laboratory 100-kW design study with 120 fuel pins, is the only prototypic component in the circuit. However, due to earlier funding constraints, a 37-pin partial-array of the core, including the central three rings of fuel pins (pin and flow path dimensions are the same as those in the full design), was selected for fabrication and test. This Technical Publication summarizes the design and integration of the pumped liquid metal Li flow circuit as of May 1, 2005. This supplement contains drawings, analysis, and calculations
Godfroy, Thomas J.↗
A power semiconductor test circuit with reduced power requirements
Switching circuit utilizing silicon controlled rectifier reduces input power requirements normally associated with testing power semiconductors in an operational type mode. Circuit alleviates problems of inaccessibility, lack of large amounts of power, physical size of power resistors, wiring, and heat generation.
Been, J. F.↗
Modifications to the Fission Surface Power Primary Test Circuit (FSP-PTC)
An actively pumped alkali metal flow circuit, designed and fabricated at the NASA Marshall Space Flight Center, underwent a range of tests at MSFC in early 2007. During this period, system transient responses and the performance of the liquid metal pump were evaluated. In May of 2007, the circuit was drained and cleaned to prepare for multiple modifications: the addition of larger upper and lower reservoirs, the installation of an annular linear induction pump (ALIP), and the inclusion of a closeable orifice in the test section. Modifications are now complete and testing has resumed. Performance of the ALIp, provided by Idaho National Laboratory (INL), is the subject of the first round ofexperimentation. This paper provides a summary of the tests conducted on the original circuit, details the physical changes that have since been made to it, and describes the current test program.
Garber, Anne E.↗