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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Properties of Nb x Ti (1–x) N thin films deposited on 300 mm silicon wafers for upscaling superconducting digital circuits

Scaling superconducting digital circuits requires fundamental changes in the current material set and fabrication process. The transition to 300 mm wafers and the implementation of advanced lithography are instrumental in facilitating mature CMOS processes, ensuring uniformity, and optimizing the yield. Here, this study explores the properties of Nb x Ti (1–x) N films fabricated by magnetron DC sputtering on 300 mm Si wafers. As a promising alternative to traditional Nb in device manufacturing, Nb x Ti (1–x) N offers numerous advantages, including enhanced stability and scalability to smaller dimensions, in both processing and design. As a ternary material, Nb x Ti (1–x) N allows engineering material parameters by changing deposition conditions. The engineered properties can be used to modulate device parameters through the stack and mitigate failure modes. We report characterization of Nb x Ti (1–x) N films at less than 2% thickness variability, 2.4% T c variability and 3% composition variability. Film resistivity (140–375 Ωcm) shows a strong correlation with the film oxygen content, while the critical temperature T c (4.6 K–14.1 K) is strongly affected by film stoichiometry and its microstructure has only a moderate effect on modifying T c . Our results offer insights about the interplay between film stoichiometry, film microstructure and critical temperature.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2020

Randomization of dangling nodes in a digital circuit design to mitigate hardware trojans

Described herein are various technologies pertaining to randomizing logic associated with dangling nodes in a digital circuit design. A dangling node is an input to or output from a logic gate in the digital circuit design that is identified as not impacting a desired output of the digital circuit design. Randomizing the logic associated with a dangling node can include deleting a logic gate, adding a logic gate, replacing a logic gate with another logic gate, etc. Randomizing the logic associated with the dangling node prevents hardware trojans that may have been inserted into the circuit design from being implemented in a circuit that is generated based upon the design.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

Radiation-Hardened GaN HEMT and Cell Design, Modeling, and Fabrication for Nuclear Instrumentation Applications

Recent advances in nuclear power generation technologies show great promise for efficient, safe generation of carbon-free power in the near future. Consequently, many new generation reactor designs are being pursued by government and industry groups, including both fission- and fusion-based technologies. Radiation- and temperature-tolerant sensor technology continues to advance, yet development of the electronics/instrumentation technologies suitable for these environments have fallen behind. Industry has adequately addressed harsh environment electronics needs for low earth orbit satellites, but the much more extreme conditions associated with electronics placed near or in a reactor core remain unaddressed. This project investigates the use of gallium nitride (GaN) circuit technology to address the unique needs for sensor interface electronics and communications in reactor environments. This report provides a summary of the first year’s project activities related to developing and optimizing devices and circuits for this GaN high electronic mobility transistor (HEMT) process. Activities reported include multiple analog and digital circuit designs simulated using custom Verilog-A models generated from measured GaN devices fabricated in the target process. Digital circuit designs included fundamental logic circuits such as an inverter, NAND, NOR, AND and OR gates, as well as a 5-stage ring oscillator. Each design was simulated using an open-source SPICE simulator, and an integrated circuit layout was produced of each design for use in future fabrication. Analog circuit designs focused on the fundamental building blocks to be used to construct sensor interface and communications circuits. These included current mirrors, matched differential pairs, and a Gilbert cell mixer design, each with an associated integrated circuit layout. Layout tools used for these designs included two open-source packages—KLayout and Magic—which were customized for specific use with the OSU GaN process layers. Design rules and preliminary device extraction capabilities were built for the Magic tool to enable device extraction and subsequent netlist generation for SPICE simulation. Finally, future research directions for year two are summarized. When the year-two directions are implemented, the project will be in position to advance the state of the art in electronics for near- or in-reactor sensor interfacing and communications.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗
DOE OSTI2019

Targeted modification of hardware trojans

The use of untrusted design tools, components, and designers, coupled with untrusted device fabrication, introduces the possibility of malicious modifications being made to integrated circuits (ICs) during their design and fabrication. These modifications are known as hardware trojans. The widespread use of commercially purchased 3rd party intellectual property (3PIP) and commercial design tools extends even into trusted design flows. Unfortunately, due to the theoretical result that there is no program that can decide whether any other program will eventually halt, we know that the properties of a program, or circuit, cannot be known in advance of running it. While we can design a circuit to meet some functional specification and generate a simulation or test suite to obtain at least probabilistic confidence that the circuit implements the intended functionality, we cannot test a circuit for unintended functionality due to the combinatorially large state space. To address these concerns, we have developed a design-time method for automatically and systematically modifying portions of a design that exhibit characteristics of hardware trojans. After each modification, the functionality of the design is verified against a comprehensive simulation suite to ensure that the intended circuit functionality has not been changed. This approach can be applied to any digital circuit and does not rely on secret keys or obfuscation.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Will Stochastic Devices Play Nice With Others in Neuromorphic Hardware?: There’s More to a Probabilistic System Than Noisy Devices

Achieving brain-like efficiency in computing requires a co-design between the development of neural algorithms, brain-inspired circuit design, and careful consideration of how to use emerging devices. The recognition that leveraging device-level noise as a source of controlled stochasticity represents an exciting prospect of achieving brain-like capabilities in probabilistic neural algorithms, but the reality of integrating stochastic devices with deterministic devices in an already-challenging neuromorphic circuit design process is formidable. Here, we explore how the brain combines different signaling modalities into its neural circuits as well as consider the implications of more tightly integrated stochastic, analog, and digital circuits. Further, by acknowledging that a fully CMOS implementation is the appropriate baseline, we conclude that if mixing modalities is going to be successful for neuromorphic computing, it will be critical that device choices consider strengths and limitations at the overall circuit level.

42 ENGINEERING↗
DOE OSTI2020

Compressing deep neural networks on FPGAs to binary and ternary precision with hls4ml

We present the implementation of binary and ternary neural networks in the hls4ml library, designed to automatically convert deep neural network models to digital circuits with FPGA firmware. Starting from benchmark models trained with floating point precision, we investigate different strategies to reduce the network's resource consumption by reducing the numerical precision of the network parameters to binary or ternary. We discuss the trade-off between model accuracy and resource consumption. In addition, we show how to balance between latency and accuracy by retaining full precision on a selected subset of network components. As an example, we consider two multiclass classification tasks: handwritten digit recognition with the MNIST data set and jet identification with simulated proton-proton collisions at the CERN Large Hadron Collider. The binary and ternary implementation has similar performance to the higher precision implementation while using drastically fewer FPGA resources.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2025

Unconventional compute methods and future challenges for superconducting digital computing

Superconducting digital computing (SDC) based on Josephson junctions (JJs) offers significant potential for enhancing compute throughput and reducing energy consumption compared to conventional room-temperature CMOS-based approaches. Current superconducting logic families exhibit diverse characteristics in clocking strategies, power management, and information encoding techniques. This paper reviews recent advancements in unconventional computing methods specifically designed for superconducting digital circuits, emphasizing temporal computing and pulse-train representations. Notable techniques include race logic (RL), temporal pulse train computing (U-SFQ), and temporal multipliers, each offering unique performance and area advantages suited to superconducting implementations. Additionally, this paper reviews innovations in superconducting coarse-grain reconfigurable architectures (CGRA), superconducting-specific on-chip communication architectures, cryogenic sensor interfaces, and quantum computing control electronics. Finally, we highlight research challenges that should be addressed to facilitate the widespread adoption of superconducting digital computing.

EDA tools↗
DOE OSTI2021

Graphene nanoribbons for quantum electronics

Graphene nanoribbons (GNRs) are a family of one-dimensional (1D) materials with a graphitic lattice structure. GNRs possess high mobility and current-carrying capability, sizeable bandgap and versatile electronic properties, which make them promising candidates for quantum electronic applications. In the past 5 years, progress has been made towards atomically precise bottom-up synthesis of GNRs and heterojunctions that provide an ideal platform for functional molecular devices, as well as successful production of semiconducting GNR arrays on insulating substrates potentially useful for large-scale digital circuits. With further development, GNRs can be envisioned as a competitive candidate material in future quantum information sciences. In this Perspective, we discuss recent progress in GNR research and identify key challenges and new directions likely to develop in the near future.

36 MATERIALS SCIENCE↗
DOE OSTI2026

Flux trapping in NbTiN strips

We use scanning superconducting quantum interference device (SQUID) microscopy to image vortices in superconducting structures fabricated from NbTiN thin films. We repeatedly cool superconducting strips with different width in an applied magnetic field and image the individual vortices. From these images we determine the threshold field at which the first vortex enters a strip and the number and configuration of vortices beyond this threshold field. We model the behavior of the vortices with and without considering the effect of pinning using numerical methods to minimize the Gibbs free energy of vortices in the strips. Our measurements provide a first benchmark to investigate the flux trapping properties of NbTiN thin films directly relevant to NbTiN-based superconducting digital circuits.

Bai, Ruiheng [Cornell University] (ORCID:000000025↗
DOE OSTI2023

A Method to Probe the Interfaces in La2−xSrxCuO4-LaSrAlO4-La2−xSrxCuO4 Trilayer Junctions

C-axis trilayer cuprate Josephson junctions are essential for basic science and digital circuit applications of high-temperature superconductors. We present a method for probing the interface perfection in La2−xSrxCuO4 (LSCO)-LaSrAlO4 (LSAO)-La2−xSrxCuO4 trilayer junctions. A series of LSCO-LSAO superlattices with atomically smooth surfaces and sharp interfaces were grown by the atomic-layer-by-layer molecular beam epitaxy (ALL-MBE) technique. We have systematically varied the thickness of LSCO and LSAO layers with monolayer precision. By studying the mutual inductance and electrical transport in these superlattices, we detect the non-superconducting (“dead”) layers at the interfaces and quantify their thicknesses. Our results indicate that two optimally doped LSCO monolayers just above and below the one monolayer LSAO barrier are no longer superconducting, rendering the actual barrier thickness of five monolayers. Next, we have shown that introducing a protective highly-overdoped LSCO layer reduces the thickness of dead layers by one or two monolayers.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2026

Advancements in NbTiN based circuits for Superconducting Digital Logic

Superconducting (SC) electronics have emerged as a promising platform for high-speed, energy-efficient computing and quantum information processing. This work, centered on NbTiN, presents recent advances in material science and fabrication methods leading to significant improvements in performance, scalability and vertical integration. We specifically report on fabrication and characterization of key components, including Josephson junctions (JJs), flux trapping structures and SC interconnects. Together, these efforts represent critical steps towards realizing practical, complex, dense and large-scale SC integrated circuits.

Pokhrel, A. [Imec,Heverlee,Belgium]↗