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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2003

The Highly Robust Electrical Interconnects and Ultrasensitive Biosensors Based on Embedded Carbon Nanotube Arrays

We report on our recent breakthroughs in two different applications using well-aligned carbon nanotube (CNT) arrays on Si chips, including (1) a novel processing solution for highly robust electrical interconnects in integrated circuit manufacturing, and (2) the development of ultrasensitive electrochemical DNA sensors. Both of them rely on the invention of a bottom-up fabrication scheme which includes six steps, including: (a) lithographic patterning, (b) depositing bottom conducting contacts, (c) depositing metal catalysts, (d) CNT growth by plasma enhanced chemical vapor deposition (PECVD), (e) dielectric gap-filling, and (f) chemical mechanical polishing (CMP). Such processes produce a stable planarized surface with only the open end of CNTs exposed, whch can be further processed or modified for different applications. By depositing patterned top contacts, the CNT can serve as vertical interconnects between the two conducting layers. This method is fundamentally different fiom current damascene processes and avoids problems associated with etching and filling of high aspect ratio holes at nanoscales. In addition, multiwalled CNTs (MWCNTs) are highly robust and can carry a current density of 10(exp 9) A/square centimeters without degradation. It has great potential to help extending the current Si technology. The embedded MWCNT array without the top contact layer can be also used as a nanoelectrode array in electrochemical biosensors. The cell time-constant and sensitivity can be dramatically improved. By functionalizing the tube ends with specific oligonucleotide probes, specific DNA targets can be detected with electrochemical methods down to subattomoles.

Li, Jun↗
NASA NTRS1981

Forming electrical interconnections through semiconductor wafers

An information processing system based on CMOS/SOS technology is being developed by NASA to process digital image data collected by satellites. An array of holes is laser drilled in a semiconductor wafer, and a conductor is formed in the holes to fabricate electrical interconnections through the wafers. Six techniques are used to form conductors in the silicon-on-sapphire (SOS) wafers, including capillary wetting, wedge extrusion, wire intersection, electroless plating, electroforming, double-sided sputtering and through-hole electroplating. The respective strengths and weaknesses of these techniques are discussed and compared, with double-sided sputtering and the through-hole plating method achieving best results. In addition, hollow conductors provided by the technique are available for solder refill, providing a natural way of forming an electrically connected stack of SOS wafers.

Anthony, T. R.↗
NASA NTRS2001

Zee electrical interconnect

An interconnect, having some length, that reliably connects two conductors separated by the length of the interconnect when the connection is made but in which one length if unstressed would change relative to the other in operation. The interconnect comprises a base element an intermediate element and a top element. Each element is rectangular and formed of a conducting material and has opposed ends. The elements are arranged in a generally Z-shape with the base element having one end adapted to be connected to one conductor. The top element has one end adapted to be connected to another conductor and the intermediate element has its ends disposed against the other end of the base and the top element. Brazes mechanically and electrically interconnect the intermediate element to the base and the top elements proximate the corresponding ends of the elements. When the respective ends of the base and the top elements are connected to the conductors, an electrical connection is formed therebetween, and when the conductors are relatively moved or the interconnect elements change length the elements accommodate the changes and the associated compression and tension forces in such a way that the interconnect does not mechanically fatigue.

Rust, Thomas M.↗
NASA NTRS2003

Packaging Technology Designed, Fabricated, and Assembled for High-Temperature SiC Microsystems

A series of ceramic substrates and thick-film metalization-based prototype microsystem packages designed for silicon carbide (SiC) high-temperature microsystems have been developed for operation in 500 C harsh environments. These prototype packages were designed, fabricated, and assembled at the NASA Glenn Research Center. Both the electrical interconnection system and the die-attach scheme for this packaging system have been tested extensively at high temperatures. Printed circuit boards used to interconnect these chip-level packages and passive components also are being fabricated and tested. NASA space and aeronautical missions need harsh-environment, especially high-temperature, operable microsystems for probing the inner solar planets and for in situ monitoring and control of next-generation aeronautical engines. Various SiC high-temperature-operable microelectromechanical system (MEMS) sensors, actuators, and electronics have been demonstrated at temperatures as high as 600 C, but most of these devices were demonstrated only in the laboratory environment partially because systematic packaging technology for supporting these devices at temperatures of 500 C and beyond was not available. Thus, the development of a systematic high-temperature packaging technology is essential for both in situ testing and the commercialization of high-temperature SiC MEMS. Researchers at Glenn developed new prototype packages for high-temperature microsystems using ceramic substrates (aluminum nitride and 96- and 90-wt% aluminum oxides) and gold (Au) thick-film metalization. Packaging components, which include a thick-film metalization-based wirebond interconnection system and a low-electrical-resistance SiC die-attachment scheme, have been tested at temperatures up to 500 C. The interconnection system composed of Au thick-film printed wire and 1-mil Au wire bond was tested in 500 C oxidizing air with and without 50-mA direct current for over 5000 hr. The Au thick-film metalization-based wirebond electrical interconnection system was also tested in an extremely dynamic thermal environment to assess thermal reliability. The I-V curve1 of a SiC high-temperature diode was measured in oxidizing air at 500 C for 1000 hr to electrically test the Au thick-film material-based die-attach assembly.

Chen, Liang-Yu↗
NASA NTRS2010

Advanced Flip Chips in Extreme Temperature Environments

The use of underfill materials is necessary with flip-chip interconnect technology to redistribute stresses due to mismatching coefficients of thermal expansion (CTEs) between dissimilar materials in the overall assembly. Underfills are formulated using organic polymers and possibly inorganic filler materials. There are a few ways to apply the underfills with flip-chip technology. Traditional capillary-flow underfill materials now possess high flow speed and reduced time to cure, but they still require additional processing steps beyond the typical surface-mount technology (SMT) assembly process. Studies were conducted using underfills in a temperature range of -190 to 85 C, which resulted in an increase of reliability by one to two orders of magnitude. Thermal shock of the flip-chip test articles was designed to induce failures at the interconnect sites (-40 to 100 C). The study on the reliability of flip chips using underfills in the extreme temperature region is of significant value for space applications. This technology is considered as an enabling technology for future space missions. Flip-chip interconnect technology is an advanced electrical interconnection approach where the silicon die or chip is electrically connected, face down, to the substrate by reflowing solder bumps on area-array metallized terminals on the die to matching footprints of solder-wettable pads on the chosen substrate. This advanced flip-chip interconnect technology will significantly improve the performance of high-speed systems, productivity enhancement over manual wire bonding, self-alignment during die joining, low lead inductances, and reduced need for attachment of precious metals. The use of commercially developed no-flow fluxing underfills provides a means of reducing the processing steps employed in the traditional capillary flow methods to enhance SMT compatibility. Reliability of flip chips may be significantly increased by matching/tailoring the CTEs of the substrate material and the silicon die or chip, and also the underfill materials. Advanced packaging interconnects technology such as flip-chip interconnect test boards have been subjected to various extreme temperature ranges that cover military specifications and extreme Mars and asteroid environments. The eventual goal of each process step and the entire process is to produce components with 100 percent interconnect and satisfy the reliability requirements. Underfill materials, in general, may possibly meet demanding end use requirements such as low warpage, low stress, fine pitch, high reliability, and high adhesion.

Ramesham, Rajeshuni↗
NASA NTRS2006

Carbon Nanotube Interconnect

Method and system for fabricating an electrical interconnect capable of supporting very high current densities ( 10(exp 6)-10(exp 10) Amps/sq cm), using an array of one or more carbon nanotubes (CNTs). The CNT array is grown in a selected spaced apart pattern, preferably with multi-wall CNTs, and a selected insulating material, such as SiOw, or SiuNv is deposited using CVD to encapsulate each CNT in the array. An exposed surface of the insulating material is planarized to provide one or more exposed electrical contacts for one or more CNTs.

Li, Jun↗
NASA NTRS2007

Metallic Nanowire Interconnections for Integrated Circuit Fabrication

A method for fabricating an electrical interconnect between two or more electrical components. A conductive layer is provided on a substarte and a thin, patterned catalyst array is deposited on an exposed surface of the conductive layer. A gas or vapor of a metallic precursor of a metal nanowire (MeNW) is provided around the catalyst array, and MeNWs grow between the conductive layer and the catalyst array. The catalyst array and a portion of each of the MeNWs are removed to provide exposed ends of the MeNWs.

Ng, Hou Tee↗
NASA NTRS2017

Thermal cycling testing to failure of a ceramic column grid array package for space applications

Ceramic column grid array (CCGA) packages have been used increasingly in logic and microprocessor functions, telecommunications, flight avionics boards, payload electronics boards, engineering navigational and science cameras, electronic assemblies, and other applications, because of their inherent advantages such as high electrical interconnect density, very good thermal and electrical performance, and compatibility with standard surface-mount technology (SMT) packaging assembly processes. Because these advanced electronic packages tend to have less solder-joint strain-relief than do leaded flat-pack electronic packages, the reliability of CCGA packages in challenging thermal environments is a very important consideration for their short- and long-term use in JPL-NASA space missions. In this study, we assembled daisy chains of polyimide printed wiring boards from CCGA-interconnect packages, inspected the boards nondestructively, and then subjected them to thermal cycling to assess their reliability in thermal environments from +125°C to -40°C±25°C. The test hardware consists of a CCGA 1752 package (CN version). The package was divided into four daisy-chained sections that were electrically monitored for their continuity during thermal cycling. The CCGA 1752 package is roughly 45 mm × 45 mm with a 42-mm × 42-mm array of 80%/20% Pb/Sn columns on a 1.00-mm pitch. The resistance of the daisy-chained CCGA interconnects was continuously monitored during thermal cycling in a gaseous nitrogen environment. Electrical continuity resistance measurements as a function of thermal cycling are reported here; tests to date have shown significant change to an open circuit in daisy-chain resistance as a function of thermal cycling. The change in interconnect resistance becomes increasingly noticeable with increasing number of thermal cycles. This paper describes the experimental thermal-cycling test results of CCGA 1752 package reliability testing under an extremely wide temperature range. The first failure was observed at 1479th thermal cycle. We report the thermal-cycle reliability test data for ~2500 thermal cycles.

Ramesham, Rajeshuni↗
NASA NTRS1976

Flexible, FEP-Teflon covered solar cell module development

Techniques and equipment were developed for the large scale, low-cost fabrication of lightweight, roll-up and fold-up, FEP-Teflon encapsulated solar cell modules. Modules were fabricated by interconnecting solderless single-crystal silicon solar cells and heat laminating them at approximately 300 C between layers of optically clear FEP and to a loadbearing Kapton substrate sheet. Modules were fabricated from both conventional and wraparound contact solar cells. A heat seal technique was developed for mechanically interconnecting modules into an array. The electrical interconnections for both roll-up and fold-up arrays were also developed. The use of parallel-gap resistance welding, ultrasonic bonding, and thermocompression bonding processes for attaching interconnects to solar cells were investigated. Parallel-gap welding was found to be best suited for interconnecting the solderless solar cells into modules. Details of the fabrication equipment, fabrication processes, module and interconnect designs, environmental test equipment, and test results are presented.

Rauschenbach, H. S.↗
NASA NTRS1994

Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip

A computer module is disclosed in which a stack of glued together IC memory chips is structurally integrated with a microprocessor chip. The memory provided by the stack is dedicated to the microprocessor chip. The microprocessor and its memory stack may be connected either by glue and/or by solder bumps. The solder bumps can perform three functions--electrical interconnection, mechanical connection, and heat transfer. The electrical connections in some versions are provided by wire bonding.

Carson, John C.↗
NASA NTRS1992

Comparative evaluation of optical waveguides as alternative interconnections for high performance packaging

A detailed comparison between optical and electrical interconnections is presented, with emphasis on advantages and drawbacks of optical link utilization. The impact of attenuation, dispersive degradation, and fan out on signal integrity is discussed. Reflections from discontinuities are taken into account in the section on fan out. According to our results, there is no obvious advantage of using optical interconnections for the distribution of digital signals containing significant frequency components in excess of 10 GHz, unless substantial distances are involved, for which low dispersion optical waveguides could provide a solution. The implementation of a polyimide optical waveguide in the MCNC package is discussed.

Schacham, S. E.↗
NASA NTRS2001

Microfabricated structures with electrical isolation and interconnections

The invention is directed to a microfabricated device. The device includes a substrate that is etched to define mechanical structures at least some of which are anchored laterally to the remainder of the substrate. Electrical isolation at points where mechanical structures are attached to the substrate is provided by filled isolation trenches. Filled trenches may also be used to electrically isolate structure elements from each other at points where mechanical attachment of structure elements is desired. The performance of microelectromechanical devices is improved by 1) having a high-aspect-ratio between vertical and lateral dimensions of the mechanical elements, 2) integrating electronics on the same substrate as the mechanical elements, 3) good electrical isolation among mechanical elements and circuits except where electrical interconnection is desired.

Clark, William A.↗
NASA NTRS1974

Design guidelines for advanced LSI microcircuit packaging using thick film multilayer technology

Ceramic multilayer circuitry results from the sequential build-up of two or more layers of pre-determined conductive interconnections separated by dielectric layers and fired at an elevated temperature to form a solidly fused structure. The resultant ceramic interconnect matrix is used as a base to mount active and passive devices and provide the necessary electrical interconnection to accomplish the desired electrical circuit. Many methods are known for developing multilevel conductor mechanisms such as multilayer printed circuits, welded wire matrices, flexible copper tape conductors, and thin and thick-film ceramic multilayers. Each method can be considered as a specialized field with each possessing its own particular set of benefits and problems. This design guide restricts itself to the art of design, fabrication and assembly of ceramic multilayer circuitry and the reliability of the end product.

Peckinpaugh, C. J.↗
NASA NTRS1984

Investigation of test methods, material properties, and processes for solar cell encapsulants

Photovoltaic (PV) modules consist of a string of electrically interconnected silicon solar cells capable of producing practical quantities of electrical power when exposed to sunlight. To insure high reliability and long term performance, the functional components of the solar cell module must be adequately protected from the environment by some encapsulation technique. The encapsulation system must provide mechanical support for the cells and corrosion protection for the electrical components. The goal of the program is to identify and develop encapsulation systems consistent with the PV module operating requirements of 30 year life and a target cost of $0.70 per peak watt ($70 per square meter) (1980 dollars). Assuming a module efficiency of ten percent, which is equivalent to a power output of 100 watts per square meter in midday sunlight, the capital cost of the modules may be calculated to be $70.00 per square meter. Out of this cost goal, only 20 percent is available for encapsulation due to the high cost of the cells, interconnects, and other related components. The encapsulation cost allocation may then be stated as $14.00 per square meter, included all coatings, pottant and mechanical supports for the cells.

Source record↗
NASA NTRS1990

Thermoelectric power conversion in space

A radiatively-heated multicouple for use in the next generation of radioisotope thermoelectric generator (RTG) will employ 20 individual couples within a single cell, so that 40 n- and p-semiconductor legs will be interconnected in series. At the hot end of the RTG, the legs will be electrically interconnected using silicon molybdenum; on the cold side, the legs are interconnected by tungsten. The entire cell is then mechanically attached to a radiator, which conducts heat away and radiates it into space. Deep-space applications will use RTGs developed for vacuum operation; thermoelectric converter power systems using a unicouple configuration have flown on such missions as Pioneers 10 and 11, which used lead telluride thermoelectric converters, and Voyagers I and II, which used silicon germanium-based thermoelectrics.

Awaya, Henry I.↗
NASA NTRS2018

Interconnection of Semiconductor Devices in Extreme Environment Microelectronic Integrated Circuit Chips

A process of fabrication and the resulting integrated circuit device is made of patterned metal electrical interconnections between semiconductor devices residing on and forming extremely harsh environment integrated circuit chips. The process enables more complicated wide band gap semiconductor integrated circuits with more than one level of interconnect to function for prolonged time periods (over 1000 hours) at much higher temperatures (500 C).

Spry, David J.↗
NASA NTRS1990

Precise synchronization of phasor measurements in electric power systems

Phasors representing positive sequence voltages and currents in a power network are in the most important parameters in several monitoring, control, and protection functions in interconnected electric power networks. Recent advances in computer relaying have led to very efficient and accurate phasor measurement systems. When the phasors to be measured are separated by hundreds of miles, it becomes necessary to synchronize the measurement processes, so that a consistent description of the state of the power system can be established. Global Positioning System (GPS) transmissions offer an ideal source for synchronization of phasor measurements. The concept and implementation of this technique are described. Several uses of synchronized phasor measurements are also described. Among these are improved state estimation algorithms, state estimator enhancements, dynamic state estimates, improved control techniques, and improved protection concepts.

Phadke, Arun G.↗
NASA NTRS2002

SEE Design Guide and Requirements for Electrical Deadfacing

The purpose of this design guide is to present information for understanding and mitigating the potential hazards associated with de-mating and mating powered electrical connectors on space flight vehicles. The process of staging is a necessary function in the launching of space vehicles and in the deployment of satellites, and now in manned assembly of systems in space. During this electrical interconnection process, various environments may be encountered that warrant the restriction of the voltage and current present across the pins of an electrical connector prior to separation, mating, or in a static open non-mated configuration. This process is called deadfacing. These potentially hazardous environments encompass the obvious explosive fuel vapors and human shock hazard, to multiple Electro-Magnetic Interference (EMI) phenomena related to the rapid rate of change in current as well as exposure to Radio Frequency (RF) fields.

Berki, Joe M.↗