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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2002

Diffractive optical elements on non-flat substrates using electron beam lithography

The present disclosure describes a technique for creating diffraction gratings on curved surfaces with electron beam lithography. The curved surface can act as an optical element to produce flat and aberration-free images in imaging spectrometers. In addition, the fabrication technique can modify the power structure of the grating orders so that there is more energy in the first order than for a typical grating. The inventors noticed that by using electron-beam lithography techniques, a variety of convex gratings that are well-suited to the requirements of imaging spectrometers can be manufactured.

Maker, Paul D.↗
NASA NTRS2005

Electron-beam lithography for micro and nano-optical applications

Direct-write electron-beam lithography has proven to be a powerful technique for fabricating a variety of micro- and nano-optical devices. Binary E-beam lithography is the workhorse technique for fabricating optical devices that require complicated precision nano-scale features. We describe a bi-layer resist system and virtual-mark height measurement for improving the reliability of fabricating binary patterns. Analog E-beam lithography is a newer technique that has found significant application in the fabrication of diffractive optical elements. We describe our techniques for fabricating analog surface-relief profiles in E-beam resist, including some discussion regarding overcoming the problems of resist heating and charging. We also describe a multiple-field-size exposure scheme for suppression of field-stitch induced ghost diffraction orders produced by blazed diffraction gratings on non-flat substrates.

electron-beam lithography↗
NASA NTRS1994

Analog Phase Holograms by Electron Beam Lithography

Phase holograms have been created on the surface of a thin film of poly-methyl methacrylate (PMMA, Plexiglas) by direct-write electron beam (E-Beam) lithography. The process involves delivering a patterned exposure dose followed by partial development with a strong developer. The patterned dose derives from arbitrary computer-calculated holograms, which must be corrected for the sensitivity characteristic of the PMMA and for the effective point-spread function of the E-Beam.

phase↗
NASA NTRS2002

Fabrication of Tunnel Junctions For Direct Detector Arrays With Single-Electron Transistor Readout Using Electron-Beam Lithography

This paper will describe the fabrication of small aluminum tunnel junctions for applications in astronomy. Antenna-coupled superconducting tunnel junctions with integrated single-electron transistor readout have the potential for photon-counting sensitivity at sub-millimeter wavelengths. The junctions for the detector and single-electron transistor can be made with electron-beam lithography and a standard self-aligned double-angle deposition process. However, high yield and uniformity of the junctions is required for large-format detector arrays. This paper will describe how measurement and modification of the sensitivity ratio in the resist bilayer was used to greatly improve the reliability of forming devices with uniform, sub-micron size, low-leakage junctions.

Stevenson, T. R.↗
NASA NTRS2001

Stitching-error reduction in gratings by shot-shifted electron-beam lithography

Calculations of the grating spatial-frequency spectrum and the filtering properties of multiple-pass electron-beam writing demonstrate a tradeoff between stitching-error suppression and minimum pitch separation. High-resolution measurements of optical-diffraction patterns show a 25-dB reduction in stitching-error side modes.

Integrated optics semiconductor lasersgratings↗
NASA NTRS2003

Effect of Alignment on Transport Properties of Carbon Nanotube/Metallic Junctions

Ballistic and spin coherent transport in single walled carbon nanotubes (SWCNT) are predicted to enable high sensitivity single-nanotube devices for strain and magnetic field sensing. Based upon these phenomena, electron beam lithography procedures have been developed to study the transport properties of purified HiPCO single walled carbon nanotubes for development into sensory materials for nondestructive evaluation. Purified nanotubes are dispersed in solvent suspension and then deposited on the device substrate before metallic contacts are defined and deposited through electron beam lithography. This procedure produces randomly dispersed ropes, typically 2 - 20 nm in diameter, of single walled carbon nanotubes. Transport and scanning probe microscopy studies have shown a good correlation between the junction resistance and tube density, alignment, and contact quality. In order to improve transport properties of the junctions a technique has been developed to align and concentrate nanotubes at specific locations on the substrate surface. Lithographic techniques are used to define local areas where high frequency electric fields are to be concentrated. Application of the fields while the substrate is exposed to nanotube-containing solution results in nanotube arrays aligned with the electric field lines. A second electron beam lithography layer is then used to deposit metallic contacts across the aligned tubes. Experimental measurements are presented showing the increased tube alignment and improvement in the transport properties of the junctions.

Wincheski, Buzz↗
NASA NTRS2019

Fabrication of Phononic-Isolated Kinetic Inductance Detectors

Kinetic inductance detectors (KID) have received increased interest due to their relative ease of fabrication, low noise, and scalability to large format arrays required by next generation of astronomical telescopes. The development of KIDs has progressed rapidly, with very low noise equivalent power demonstrated by several groups and KIDs arrays implemented in several ground-based and air-borne instruments. In this paper, we describe a new fabrication process which consists of a membrane isolated KID incorporating a phononic bandgap structure tuned to block recombination phonons from escaping to the thermal bath. This architecture is designed to increase the quasi-particle lifetime and results in increased responsivity to signal photons and lower noise. These devices have been fabricated as lumped-element resonators with hafnium inductors and Nb capacitors on low stress silicon nitride and silicon-on-insulator membranes. We discuss the fabrication process, which uses a combination of sub-micron laser based direct write lithography and nanoscale electron beam lithography.

Denis, Kevin L.↗
NASA NTRS2004

Fabricating Blazed Diffraction Gratings by X-Ray Lithography

Gray-scale x-ray lithography is undergoing development as a technique for fabricating blazed diffraction gratings. As such, gray-scale x-ray lithography now complements such other grating-fabrication techniques as mechanical ruling, holography, ion etching, laser ablation, laser writing, and electron-beam lithography. Each of these techniques offers advantages and disadvantages for implementing specific grating designs; no single one of these techniques can satisfy the design requirements for all applications. Gray-scale x-ray lithography is expected to be advantageous for making gratings on steeper substrates than those that can be made by electron-beam lithography. This technique is not limited to sawtooth groove profiles and flat substrates: various groove profiles can be generated on arbitrarily shaped (including highly curved) substrates with the same ease as sawtooth profiles can be generated on flat substrates. Moreover, the gratings fabricated by this technique can be made free of ghosts (spurious diffraction components attributable to small spurious periodicities in the locations of grooves). The first step in gray-scale x-ray lithography is to conformally coat a substrate with a suitable photoresist. An x-ray mask (see Figure 1) is generated, placed between the substrate and a source of collimated x-rays, and scanned over the substrate so as to create a spatial modulation in the exposure of the photoresist. Development of the exposed photoresist results in a surface corrugation that corresponds to the spatial modulation and that defines the grating surface. The grating pattern is generated by scanning an appropriately shaped x-ray area mask along the substrate. The mask example of Figure 1 would generate a blazed grating profile when scanned in the perpendicular direction at constant speed, assuming the photoresist responds linearly to incident radiation. If the resist response is nonlinear, then the mask shape can be modified to account for the nonlinearity and produce a desired groove profile. An example of grating grooves generated by this technique is shown in Figure 2. A maximum relative efficiency of 88 percent has been demonstrated.

Mouroulis, Pantazis↗
NASA NTRS2005

In Situ Electrochemical Deposition of Microscopic Wires

A method of fabrication of wires having micron and submicron dimensions is built around electrochemical deposition of the wires in their final positions between electrodes in integrated circuits or other devices in which the wires are to be used. Heretofore, nanowires have been fabricated by a variety of techniques characterized by low degrees of controllability and low throughput rates, and it has been necessary to align and electrically connect the wires in their final positions by use of sophisticated equipment in expensive and tedious post-growth assembly processes. The present method is more economical, offers higher yields, enables control of wire widths, and eliminates the need for post-growth assembly. The wires fabricated by this method could be used as simple electrical conductors or as transducers in sensors. Depending upon electrodeposition conditions and the compositions of the electroplating solutions in specific applications, the wires could be made of metals, alloys, metal oxides, semiconductors, or electrically conductive polymers. In this method, one uses fabrication processes that are standard in the semiconductor industry. These include cleaning, dry etching, low-pressure chemical vapor deposition, lithography, dielectric deposition, electron-beam lithography, and metallization processes as well as the electrochemical deposition process used to form the wires. In a typical case of fabrication of a circuit that includes electrodes between which microscopic wires are to be formed on a silicon substrate, the fabrication processes follow a standard sequence until just before the fabrication of the microscopic wires. Then, by use of a thermal SiO-deposition technique, the electrodes and the substrate surface areas in the gaps between them are covered with SiO. Next, the SiO is electron-beam patterned, then reactive-ion etched to form channels having specified widths (typically about 1 m or less) that define the widths of the wires to be formed. Drops of an electroplating solution are placed on the substrate in the regions containing the channels thus formed, then the wires are electrodeposited from the solution onto the exposed portions of the electrodes and into the channels. The electrodeposition is a room-temperature, atmospheric-pressure process. The figure shows an example of palladium wires that were electrodeposited into 1-mm-wide channels between gold electrodes.

Yun, Minhee↗
NASA NTRS2008

Capillography of Mats of Nanofibers

Capillography (from the Latin capillus, 'hair', and the Greek graphein, to write ) is a recently conceived technique for forming mats of nanofibers into useful patterns. The concept was inspired by experiments on carpetlike mats of multiwalled carbon nanotubes. Capillography may have the potential to be a less-expensive, less-time-consuming alternative to electron-beam lithography as a means of nanoscale patterning for the fabrication of small devices and instruments. In capillography, one exploits the lateral capillary forces exerted on small objects that pierce the surface of a liquid. If the small objects are identical, then the forces are always attractive. Two examples of the effects of such forces are the agglomeration of small particles floating on the surface of a pond and the drawing together of hairs of a wet paintbrush upon removal of the brush from water. Because nanoscale objects brought into contact remain stuck together indefinitely due to Van der Waals forces, patterns formed by capillography remain even upon removal of the liquid. For the experiments on the mats of carbon nanotubes, a surfactant solution capable of wetting carbon nanotubes (which are ultra-hydrophobic) was prepared. The mats were wetted with the solution, then dried. Once the mats were dry, it was found that the nanotubes had become ordered into various patterns, including nestlike indentations, trenches, and various combinations thereof. It may be possible to exploit such ordering effects through controlled wetting and drying of designated portions of mats of carbon nanotubes (and, perhaps, mats of nanofibers of other materials) to obtain patterns similar to those heretofore formed by use of electron-beam lithography. For making patterns that include nestlike indentations, it has been conjectured that it could be possible to control the nesting processes by use of electrostatic fields. Further research is needed to understand the physics of the patterning processes in order to develop capabilities to control patterns formed in capillography.

Noca, Flavio↗
NASA NTRS1994

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

Sewell, James S.↗
NASA NTRS2007

Focal-Plane Arrays of Quantum-Dot Infrared Photodetectors

Focal-plane arrays of semiconductor quantum-dot infrared photodetectors (QDIPs) are being developed as superior alternatives to prior infrared imagers, including imagers based on HgCdTe devices and, especially, those based on quantum-well infrared photodetectors (QWIPs). HgCdTe devices and arrays thereof are difficult to fabricate and operate, and they exhibit large nonunformities and high 1/f (where f signifies frequency) noise. QWIPs are easier to fabricate and operate, can be made nearly uniform, and exhibit lower 1/f noise, but they exhibit larger dark currents, and their quantization only along the growth direction prevents them from absorbing photons at normal incidence, thereby limiting their quantum efficiencies. Like QWIPs, QDIPs offer the advantages of greater ease of operation, greater uniformity, and lower 1/f noise, but without the disadvantages: QDIPs exhibit lower dark currents, and quantum efficiencies of QDIPs are greater because the three-dimensional quantization of QDIPs is favorable to the absorption of photons at normal or oblique incidence. Moreover, QDIPs can be operated at higher temperatures (around 200 K) than are required for operation of QWIPs. The main problem in the development of QDIP imagers is to fabricate quantum dots with the requisite uniformity of size and spacing. A promising approach to be tested soon involves the use of electron-beam lithography to define the locations and sizes of quantum dots. A photoresist-covered GaAs substrate would be exposed to the beam generated by an advanced, high-precision electron beam apparatus. The exposure pattern would consist of spots typically having a diameter of 4 nm and typically spaced 20 nm apart. The exposed photoresist would be developed by either a high-contrast or a low-contrast method. In the high-contrast method, the spots would be etched in such a way as to form steep-wall holes all the way down to the substrate. The holes would be wider than the electron beam spots perhaps as wide as 15 to 20 nm, but may be sufficient to control the growth of the quantum dots. In the low-contrast method, the resist would be etched in such a way as to form dimples, the shapes of which would mimic the electron-beam density profile. Then by use of a transfer etching process that etches the substrate faster than it etches the resist, either the pattern of holes or a pattern comprising the narrow, lowest portions of the dimples would be imparted to the substrate. Having been thus patterned, the substrate would be cleaned. The resulting holes or dimples in the substrate would serve as nucleation sites for the growth of quantum dots of controlled size in the following steps. The substrate would be cleaned, then placed in a molecular-beam-epitaxy (MBE) chamber, where native oxide would be thermally desorbed and the quantum dots would be grown.

Gunapala, Sarath↗
NASA NTRS1998

New Convex Grating Types for Concentric Imaging Spectrometers

The properties of convex gratings fabricated by electron-beam lithography are investigated. Three grating types are shown. These gratings allow the optical designer to fully realize the considerable advantages of concentric spectrometer forms.

spectrometers concentric imaging electron beam↗