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To effectively use “Hardware in the Loop” (HIL) methodologies in the development of test systems, the tester architecture must be capable of seamlessly switching between executing tests against simulations and real units. This report describes initial attempts to build an integrated system with these capabilities.
This work presents an automatic extruder as a research experience for undergraduate students. The system offers a user-friendly approach to preparing vesicles, such as liposomes or polymersomes, with a defined size and polydispersity properties crucial for research in biology and macromolecules. It comprises two syringe pumps connected by a membrane filter. The setup is controlled by software. Compared to manual extrusion, this automated system provides advantages, such as precisely controlled variables. The project describes a tool to enhance undergraduate learning in science and engineering laboratories. Building an automatic extruder serves as a simplified model of a complex industrial process. It offers a clear advantage: automating a well-understood manual extrusion process. To make this project accessible, it is broken down into three manageable tasks: software development, hardware assembly, and testing procedures. This breakdown describes the software created, the hardware components used, and the testing procedures conducted for this project. All project data, including software code, testing data, and procedures, are freely available online. This allows undergraduate students to not only begin their own projects but also contribute to this educational instrument’s ongoing development.
This document describes the development of a field programable gate array (FPGA) radio frequency system on a chip (RF SoC) adaptation and evaluation of the single-board device to perform both Frequency Domain Reflectometry (FDR) and Spread Spectrum Time Domain Reflectometry (SSTDR) for offline and online cable testing. The work builds on and leverages the work of Pacific Northwest National Laboratory (PNNL) in airport millimeter wave technology by using the same development hardware employed in that program. The work is performed under sponsorship from the U.S. Department of Energy (DOE) Light Water Reactor Sustainability (LWRS) program and the task objective is to confirm and demonstrate feasibility to adapt FPGA technology for a cost-effective multiplexed single-board electronic module to perform cable tests that are equivalent to commercial and laboratory test instruments for FDR and SSTDR cable tests. The developed 2-channel (extendable to 7 channels) system was compared to dedicated and proven test instruments and shown to produce equivalent results on a range of cables and with a range of damage types. The FPGA reflectometry test board is one of several technologies that could facilitate implementation of online monitoring of safety critical cable systems.
This tutorial offers a pedagogical guide to hybrid quantum processors that integrate discrete-variable (DV) qubits and continuous-variable (CV) oscillators. Aimed at computer scientists, engineers, and physicists, it provides an overview of the experimental, algorithmic, and architectural aspects of this novel and rapidly developing hardware model. Experimental realizations of this model include superconducting, trapped-ion, and neutral-atom platforms. By combining DV and CV components, hybrid oscillator-qubit processors enable a powerful new paradigm that offers complementary strengths for quantum control, error correction, computation, and simulation. Working toward the goal of a full-stack system connecting applications to CV-DV hardware, we define and formulate abstract machine models and instruction set architectures. These essential abstractions enable codesign of hardware and software, and resource estimation for exploring the potential of current and future hardware for computational and simulation tasks. Using these abstractions, we present both new and existing examples that illustrate the benefits of hybrid CV-DV processors relative to traditional DV-only hardware in computation as well as quantum simulation of physical models. Examples include algorithms for transferring states between DV and CV systems, performing the quantum Fourier transform, and simulation of lattice gauge theories. Relative to qubit-only hardware, the bosonic degrees of freedom natively available in hybrid architectures can substantially reduce the circuit complexity of simulations for physical models containing bosons. A key technique is the extension of quantum signal processing ideas to CV-DV systems. This work is intended to serve as a timely and comprehensive guide to this relatively unexplored yet promising approach to quantum computation and to provide a road map to guide future development.
One of the most striking measurements taken during DOE’s EGS Collab project at the 4850-foot depth location was the so-called ‘sewer cam’, which enabled direct visualization of the flow of water into the production well through fractures during the stimulation. The ability to see directly which fractures were flowing and (roughly) how much was a breakthrough in understanding the topology of the created fracture network. Achieving this kind of fracture flow imaging at FORGE would be more challenging because of the 225°C temperature, but equally or even more valuable if it could be achieved. In 2017, a joint project between Sandia and Stanford developed a downhole tool concept to measure the enthalpy of multiphase fluid entering a geothermal well from individual fractures (Gao et al., 2017). For the FORGE project, measuring enthalpy is of less interest because the fluid is expected to be single-phase liquid water. However, the foundation of the device was the measurement of chloride ion concentration, which could form the basis for a direct measurement of inflow from fractures. During the 2017 project, this novel chloride sensing system was implemented into a laboratory test instrument, and we confirmed the capability of the system to measure the ion concentration of fluid entering a model wellbore through a small entry port. The wellbore was a 6-inch diameter model well, and the port was approximately 0.08 inch (2mm) in diameter. The device could measure the chloride concentration accurately even when the well was flowing in a bubbly flow. Given its accuracy, the tool should be able to identify locations of water entering the wellbore even if the ion concentration differs only slightly from that of the water in the well. It is likely that different fractures may flow slightly different chloride concentrations, which would make it feasible to detect individual fractures as well as to estimate the volume of their flow. Ultimately, we could also recognize different fractures flowing back significantly different ion concentrations after fracturing in the FORGE wells. This could be realized by adding different ions in the fracturing fluids in different fractures created at different stages of stimulation (and modifying the tool to include different ion specificity). Sandia’s tool was shown during the study to have the capability to withstand the 225°C temperature, and the electrochemical sensing elements were tested in the laboratory to 225°C at 1500 psia for 24 hours. An early implementation of the fully integrated downhole electrochemical tool, including high-temperature electronics, robust housing, and wireline truck interface, had previously been constructed and tested successfully at Sandia; thus, hardware development tasks focused on advancing the technology readiness level (TRL) of this promising technology for FORGE deployment, rather than on developing a new scientific basis for its operation. The data collection electronics in this tool allowed for several other sensors (pressure, temperature, flow spinner) to be implemented in parallel as well. The research was a new collaboration between Stanford and Sandia to modify and refine the tool for FORGE deployment, to make the downhole measurements, and to characterize the evolving fractures.
This paper presents the second part of a study in which the leading-edge and suction surface of a compressor blade was modified to delay onset of phase change for sCO 2 compressors operating near the critical point. Using a first-of-its-kind apparatus for the measurement of sCO 2 flow fields, Particle Image Velocimetry (PIV) is used for local flow field measurements of two compressor blade geometries: the modified “biased-wedge,” and a conventional constant thickness blade. Utilizing the developed hardware, the feasibility of a simple, laser-based diagnostic for qualitatively measuring liquid phase regions, is also presented. The design of the optical diagnostics rig, a discussion of numerous challenges, and necessary considerations involved in performing optical-based measurements like PIV, in sCO 2 , are discussed. Velocity field measurements for the modified compressor profile show a much lower suction peak compared to a conventional blade. Furthermore, these results validate numerical results at the tested conditions, where the suction side profile of the biased wedge works to minimize the local pressure gradient.
Hardware in the Loop (HIL) testing methodologies have become widespread in industry. Typically, they focus on developing control algorithms for systems such as autonomous vehicles or aircraft. An oft overlooked aspect of product development is the design and fabrication of a test system for validating that the product meets requirements. Abstractly, a test system differs little from a control system—testers provide signals to the unit, monitor feedback, and base decisions on the results. While the time scales may differ, the functionalities are conceptually similar. Viewed in this light, it becomes natural to extend HIL approaches to tester development. By replacing a physical unit with a proxy model deployed to a real-time or pseudo real-time target, test systems can be developed in parallel with the design and fabrication of a first production unit. This saves considerable time in the life cycle from conceptual design to realized product. This manuscript demonstrates the process flow using a capacitive discharge unit as an exemplar.
The RF Test Facility (RFTF) at the Spallation Neutron Source (SNS) is used for the conditioning of RF compo-nents such as ceramic vacuum windows and power cou-plers prior to their installation in the H- ion linear accel-erator. This process exposes components to high-power RF fields and thermal cycling to improve performance and remove surface impurities. To automate and optimize this process, a Python-based EPICS control system was developed alongside targeted hardware upgrades. The system enables real-time monitoring and control of RF power levels, temperature, and vacuum pressure. A user-friendly graphical interface was implemented using CS-Studio (Phoebus), allowing operators to adjust parameters and collect data efficiently. The system integrates a High-Power Protection Module (HPM) for interlocks based on vacuum and arc detection, ensuring safe operation. These upgrades have significantly improved the efficiency, accuracy, and safety of RF conditioning at the SNS RFTF. This paper describes the updated RF conditioning sys-tem, highlighting the software and hardware develop-ments and their application in support of the Proton Pow-er Upgrade (PPU) project.
Hardware-in-the-Loop (HIL) methodologies for test system development often require simulations capable of running at MHz speeds on FPGAs. The stringent memory and speed constraints necessitate compromises between model fidelity and execution speed. Numerically solving the underlying governing equations represents the highest accuracy, but slowest responding approach. By storing pre-determined results in look-up-tables (LUT), one can balance speed and accuracy.
ICARUS (Imaging Cosmic And Rare Underground Signals) is a liquid argon time projection chamber (LArTPC) detector that pursues the sterile neutrino, which relies on accurate simulations of neutrino-argon interactions. REDTOP (Rare Eta Decays To Observe new Physics) is a proposed low-energy, high-intensity meson factory designed to explore rare $\eta$/$\eta'$ meson decays and probe physics beyond the Standard Model. As a next-generation experiment, this requires both accurate simulations and innovative detector technologies. This project contributes to both ICARUS, from a simulation perspective, and REDTOP, from both a simulation and detection perspective, through the event generation of lepton-nucleon interactions and the physical enhancement of the calorimeter technology within the REDTOP detector. We developed an interface between ACHILLES (A CHIcago Land Lepton Event Simulator), a theory-driven lepton-level event generator, and GENIE, a robust event generator framework used for neutrino physics. By incorporating the precise theoretical cross-section calculations of ACHILLES into the experimental realism of GENIE, the interface allows for improved accuracy of neutrino-nucleon simulations, which can be adapted for the proton beam specifications of the REDTOP meson factory as well as for the ICARUS experiment. In parallel, we developed an improved prototype for the ADRIANO2 (A Dual Readout Integrally Active Non-segmented Option) dual-readout calorimeter tiles for the REDTOP detector. To improve the efficiency of the lead-glass tiles trapping Cherenkov light for energy reconstruction and particle identification, we optimized the application of a highly reflective coating. Through viscosity and thickness control, masking, and a custom spray technique, we refined the coating process to reduce surface defects and improve light yield. Together, these efforts strengthen the ICARUS neutrino program and REDTOP's capability of detecting rare decay events.
Superconducting qubits are highly sensitive to ionizing radiation, which can induce correlated errors and limit scalable fault-tolerant quantum computing. In particular, cosmic-ray muons can deposit energy in the substrate, generating phonon bursts that break Cooper pairs and produce quasiparticles, leading to correlated decoherence events across multiple qubits. We present the development of a cryogenic muon tagging system based on Kinetic Inductance Detectors (KIDs) and its integration with superconducting quantum hardware. Originally developed within the ACE-SuperQ project and validated as a standalone detector, the system demonstrated a muon tagging efficiency of approximately 90% and excellent agreement with Monte Carlo simulations. Building on this validation, the tagging system has been integrated with a multi-qubit superconducting chip operated in a dilution refrigerator. The detector configuration consists of a multi-layer KID stack arranged above and below the quantum device, enabling time-coincident identification of muon-induced events within the same cryogenic environment. The integrated setup has been successfully commissioned, enabling simultaneous operation of the qubit chip and the muon tagging system. A first measurement campaign has been carried out, and preliminary data show time-correlated events between the muon tagging detectors and the qubit readout. A quantitative analysis of radiation-induced effects on qubit performance is currently ongoing. This work represents a step toward the implementation of event-level radiation tagging as a tool for characterizing and potentially mitigating correlated errors in superconducting quantum processors, while establishing a modular platform for future studies at the interface between particle physics and quantum information science.
In our previous work, an adaptive measurement-driven wide-area damping controller (WADC) for suppressing inter-area oscillations has been proposed and a hardware prototype was developed and validated through hardware-in-the-loop tests. As a continuation of the work, this paper introduces a WADC software prototype to handle the realistic challenges for field implementation in the control room of the power grid. The WADC software is developed and operated as an openPDC adapter with a graphical user interface (GUI) to monitor the WADC inputs and output, the communication delays and other variables. The software prototype has been fully tested through an enhanced hardware-in-the-loop (HIL) test setup. Its performance is verified under various realistic communication uncertainties, such as random time delays and data losses, with different communication protocols. The experiment results have proven the WADC software can deliver sufficient damping to suppress the targeted oscillation mode in handling various communication uncertainties for future field deployment.
Abstract Spiking neural networks and neuromorphic hardware platforms that simulate neuronal dynamics are getting wide attention and are being applied to many relevant problems using Machine Learning. Despite a well-established mathematical foundation for neural dynamics, there exists numerous software and hardware solutions and stacks whose variability makes it difficult to reproduce findings. Here, we establish a common reference frame for computations in digital neuromorphic systems, titled Neuromorphic Intermediate Representation (NIR). NIR defines a set of computational and composable model primitives as hybrid systems combining continuous-time dynamics and discrete events. By abstracting away assumptions around discretization and hardware constraints, NIR faithfully captures the computational model, while bridging differences between the evaluated implementation and the underlying mathematical formalism. NIR supports an unprecedented number of neuromorphic systems, which we demonstrate by reproducing three spiking neural network models of different complexity across 7 neuromorphic simulators and 4 digital hardware platforms. NIR decouples the development of neuromorphic hardware and software, enabling interoperability between platforms and improving accessibility to multiple neuromorphic technologies. We believe that NIR is a key next step in brain-inspired hardware-software co-evolution, enabling research towards the implementation of energy efficient computational principles of nervous systems. NIR is available atneuroir.org
Quantum computers offer an intriguing path for a paradigmatic change of computing in the natural sciences and beyond, with the potential for achieving a so-called quantum advantage—namely, a significant (in some cases exponential) speedup of numerical simulations. The rapid development of hardware devices with various realizations of qubits enables the execution of small-scale but representative applications on quantum computers. In particular, the high-energy physics community plays a pivotal role in accessing the power of quantum computing, since the field is a driving source for challenging computational problems. This concerns, on the theoretical side, the exploration of models that are very hard or even impossible to address with classical techniques and, on the experimental side, the enormous data challenge of newly emerging experiments, such as the upgrade of the Large Hadron Collider. In this Roadmap paper, led by CERN, DESY, and IBM, we provide the status of high-energy physics quantum computations and give examples of theoretical and experimental target benchmark applications, which can be addressed in the near future. Having in mind hardware with about 100 qubits capable of executing several thousand two-qubit gates, where possible, we also provide resource estimates for the examples given using error-mitigated quantum computing. The ultimate declared goal of this task force is therefore to trigger further research in the high-energy physics community to develop interesting use cases for demonstrations on near-term quantum computers.
The FNCL investigations team at Lawrence Livermore National Laboratory (LLNL) has completed research and development of hardware, signal processing, and analysis tools to enhance the measurement capabilities of both the current CAEN SyS VeryFuel Fast Neutron Collar (FNCL) instrument and a next-generation FNCL prototype. The team successfully built and commissioned the LLNL Demonstrator System: a fully integrated, three-panel detector system featuring higher segmentation, plastic scintillators (EJ-276D), Silicon Photomultipliers (SiPMs), no high-voltage requirement, a reduced electronic footprint, and the LLNL-developed Gaussian Mixture Model Pulse Shape Discrimination (GMM-PSD) signal processing. An extensive experimental campaign was conducted at LLNL’s Inherently Safe Subcritical Assembly (ISSA) facility using both the baseline FNCL and the LLNL Demonstrator. The campaign results validated system performance, calibration stability, and the effectiveness of advanced signal processing and analysis algorithms in a relevant environment.
Spiking neural networks (SNNs) running on neuromorphic computers offer an energy-efficient alternative for AI tasks. Recently, spiking graph neural networks (S-GNNs) have been shown to produce encouraging results on benchmark citation network datasets such as Cora, CiteSeer, and PubMed for node classification tasks. These S-GNNs were run on SNN simulators only because they contain up to tens of thousands of neurons and up to millions of synapses, translating poorly to neuromorphic hardware. Therefore, in this paper, we create a suite of benchmark datasets from the CiteSeer dataset that can be accommodated on current neuromorphic hardware platforms. Our contribution consists of a collection of three datasets. First, we have an induced subgraph of CiteSeer, which we call MiniSeer, containing 2110 papers, 3604 binary features, and 6 topics. Second, MicroSeer is a very small dataset consisting of 84 papers, 1227 features, and 6 topics. Lastly, BiteSeer is a collection of 15 binary classification datasets. We present creation of these datasets along with accuracies, running times, and spike counts when simulated. We believe that our results in this paper will be used by the neuromorphic community to benchmark, test, and develop neuromorphic hardware and simulators.
Many recent efforts in developing hardware-accelerated spiking neural networks (SNNs) are characterized by deep co-design between algorithms, architectures, and devices. Architectural advances overcome device constraints by coupling together many small resistive-RAM (ReRAM) crossbars via a network-on-chip (NoC) for neuromorphic component operation. Concurrently, improved SNN training methods increase accuracy and structural sparsity in networks despite growing problem sizes. Finally, compilers leverage these attributes to minimize area and inter-crossbar communication while mapping large SNNs to sophisticated architectures. However, for compiler-driven co-design to realize increasingly complex and profitable optimizations, a compile-time view of power consumption is critical. We present PowerMappeR to express and optimize over mapping-, architecture-, and device-specific power consumption information. By modeling the dynamic power of well-established components, we develop an integer linear programming (ILP)-based, encoding-agnostic, parametric power estimation model. Using this model, we demonstrate practical improvements in area and inter-crossbar communication by 0%–9.5% and 1.4%–5.1%, respectively. We also limit hotspot formation during optimization, achieving comparable or better results in targeted metrics with up to 96.4%–97.1% restriction of hotspot magnitude. Finally, we introduce profile-guided formulations to reduce worst-case and expected-case hotspot magnitude by 40.7%–69.5% and 40.6%–56.3%, respectively. Optimizing worst-case hotspot magnitude incidentally improves expected-case magnitude by 10.85%–33.45%. Reciprocally, optimizing expected-case magnitude incidentally improves worst-case magnitude by 4.33%–39.87%. Validation against hardware simulators confirms that PowerMappeR can decrease dynamic power consumption by 12.6%–27.3%.
With the rise of artificial intelligence, the popularization of deep learning, and a constantly evolving industry, the demand for flexible and efficient tools has never been greater. As algorithms grow more complex, their runtime and energy consumption increase exponentially. Customized hardware accelerators, long used for specific mathematical operations, remain essential for managing modern applications' computational and power demands. Hardware accelerators can speed up complex computations by orders of magnitude, but their manual design and verification processes are often challenging and time-consuming. High-Level Synthesis (HLS) provides a solution by transforming high-level algorithm descriptions, typically written in C++ or SystemC, into synthesizable RTL suitable for hardware implementation. This approach reduces development time for RTL engineers while offering flexibility beyond what traditional handwritten RTL can provide. We extended this capability to the machine-learning domain with the open-source framework hls4ml, which allows neural networks trained in Python frameworks like Tensorflow or PyTorch to be synthesized into efficient hardware representations for the traditional FPGA and ASIC flows. This breakthrough addresses the growing need for reduced design turnaround and easy verification of ML hardware accelerators with low latency and power efficiency constraints. During this tutorial, we will demonstrate how Python complements HLS by simplifying the ML design process, bridging the gap between software and hardware development. Attendees will explore how we translate neural networks modeled in Python into fixed-point C++ models suitable for HLS workflows. We will dive into strategies like Value-Range Analysis and Quantization-Aware Training, which optimize these designs for deployment and evaluate their accuracy, power consumption, and energy efficiency. To exemplify these concepts, experts from Fermilab will share their experiences applying this technology to high-energy physics experiments, where real-time, low-latency processing is critical. Over the years, Fermilab engineers have demonstrated how deep neural networks, optimized for hardware using hls4ml, can meet the stringent requirements of trigger systems at the CERN Large Hadron Collider. These systems rely on rapid decision-making to process immense data volumes while retaining only the most relevant events for further analysis. The application of hls4ml has also been extended to innovative technologies like smart pixel arrays. These smart pixels integrate ML inference capabilities directly into sensor devices, enabling localized data processing at the pixel level. This approach drastically reduces the need to transmit raw data to external processing units, significantly decreasing power consumption and latency. By embedding neural networks within the pixel architecture, the smart pixels can identify and prioritize relevant data in real time, providing a highly efficient solution for edge computing in scenarios such as particle detectors and imaging systems. Fermilab's work highlights the potential of hardware-accelerated ML in scenarios where both speed and power efficiency are mission-critical. Through this tutorial, attendees will gain valuable insights into the challenges and solutions of deploying ML in hardware. Understanding how HLS and hls4ml streamline the development of neural network-based hardware accelerators is fundamental for the industry's future. Participants will learn how these technologies are shaping the future of AI and scientific computing.