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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS2020

An Embedded Planar-Foil Capacitor Material, FPGA Based Interposer, Aimed at Improving System Performance and Reduced Board Size for Space Based Electronics

This paper presents our work to date in developing, and testing an embedded planar-foil capacitor based interposer intended to be integrated together with high-density components such as Field Programmable Gate Arrays (FPGAs), and Application Specific Integrated Circuit (ASIC) applications. FPGA devices typically have a large number of I/O and power pins. The high speed enabled by these devices requires a large number of discrete bypass capacitors as close as possible to the power pins. These capacitors take up a considerable amount of the board area on the application circuit board. Our interposer replaces these components freeing up space of traditional bypass capacitors for other circuitry. Our Interposer focuses on the needs of Micro Semi’s RTG4 FPGA. We developed the interposer using COTS embedded foil capacitors. The Interposer is customized to the capacitance requirements for each of the FPGA banks. We evaluated three foil manufactures Oak Mitsui, 3M and TDK. The three different designs were evaluated, but we will focus on the Oak-Mitsui based Interposer that we constructed and tested. Through simulations, we validate the horizontal and vertical interconnect inductances, that FPGA decoupling requirements are met. The use of the interposer results in an overall reduction in our Printed Wiring Board (PWB) area.

Hunter, Don J↗
DOE OSTI2021

A Double-side Cooled SiC MOSFET Power Module with Sintered-silver Interposers: I. Design, Simulation, Fabrication, and Performance Characterization

Planar, double-side cooled power modules are emerging in electric-drive inverters because of their low profile, better heat extraction, and lower package parasitic inductances. However, there is still concern about their reliability due to the rigid interconnection between the device chips and two substrates of the power module. In this paper, a porous interposer made of low-temperature sintered silver is introduced to reduce the thermo-mechanical stresses in the module. A double-side cooled half-bridge module consisting of two 1200 V, 149 A SiC MOSFETs was designed, fabricated, and characterized. By using the sintered-Ag instead of solid copper interposers, our simulation results showed that at a total power loss of 200 W, the thermo-mechanical stress at the most vulnerable interfaces (interposer-attach layer) was reduced by 42 % and in the SiC MOSFET by 50 % with a trade-off of only 3.6 % increase in junction temperature. The sintered-Ag interposers were readily fabricated into desired dimensions without post-machining and did not require any surface finishing for die-bonding and substrate interconnection by silver sintering. Here, the porous interposers were also deformable under a low force or pressure, which helped to accommodate chip thickness and/or substrate-to-substrate gap variations in the planar module structure, thus simplifying module fabrication. Experimental results on the electrical performance of the fabricated SiC modules validated the success of using the porous silver interposers for fabricating planar, double-side cooled power modules.

42 ENGINEERING↗
DOE OSTI2023

Micro-Transfer Printing of Repeaters on Passive Interposer

Silicon-based sensors are central to particle physics experiments and particle tracking detectors. New-generation Large Focal Plane Arrays (LFPAs) cover areas that extend beyond several square meters. Distributing power and transporting data across such areas while maintaining good signal integrity is a complicated challenge. Tiling the detector on an organic interposer would be far too expensive and take too much space while offering little to no advantage regarding signal integrity. Passive silicon interposers are much less expensive and more integrable but would worsen signal integrity because of their inherent higher dielectric constant. Active interposers are a good compromise from the economic and signal integrity standpoint; unfortunately, their yield trends to zero for areas greater than a reticle size, making this technology incompatible with our application. NHanced proposes to duplicate the behavior of a high-yield, low-cost active interposer by printing active microcomponents on a passive interposer with our die-to-wafer micro-transfer printing (MTP) technology. This resolves the signal integrity and power distribution limitations. In Phase I, we designed and simulated analog and digital repeaters to be MTPed onto a passive silicon interposer test wafer.

2.5D↗
DOE OSTI2018

High Density Chip Interconnect Technology Using High Density Glass Interposers

Demands for high density and high speed interconnect solutions are not satisfied by current technology offerings. Platforms such as printed circuit boards (PCBs), ceramic substrates and silicon interposers don’t provide the small form factor nor the I/O density to support 5G or 1Tbps gigabit ethernet solutions. Current solutions also don’t support die to die assembly with integrated tiled solutions for wide area and fanout solutions for lager data and signal processing. A solution with through vias provides an order of magnitude or smaller density supporting much higher density attach and assembly By fabricating a very fine pitch metal filled through glass via solution it’s possible to deliver the necessary improvements in performance, reliability, even higher data speed rates with smaller area and much denser geometries. There are a number of opportunities across a wide variety of industries for through glass interposers as they become the replacement for printed circuit boards (PCBs) and ceramic substrates. The broad array of opportunities include renewable energy, medical electronics (ME), defense electronics (DE)/space and consumer electronics (CE), but likely will impact every industry and market segment. Compared to PCBs, through glass via (TGV) solutions provide the next generation platform for semiconductor assembly improvements. The ability to generate lines, spaces, trenches and vias similar to wafer level geometries delivers wired solutions one to two orders of magnitude smaller than traditional organic PCB and ceramic substrate offerings. Higher density connections also include the thru vias that connect multiple metal layers, fanout. It’s possible to deliver filled metal vias that are 20um diameter with much tighter pitch than can be offered with PCB. Our goal is to provide 20um diameter and smaller via, 50um and smaller pitch, and aspect ratios at 25:1 and greater with hermetically metal filled vias. The goal of CVI is to replace or eliminate PCBs, ceramic substrate and through silicon vias (TSV) providing a glass interposer with metal filled, fiber plugged and/or optional wireless interconnectivity. The end plan is to deliver a glass substrate platform that provides improved electrical performance, versatility, inertness, and much improved cost and cycle time (development, drawing, and delivery) to performance in the form of small millimeter sized substrates or full 8” wafer substrates. Glass delivers an improvement over silicon thru vias (TSV) in the number of processing steps, cost, reliability and cycle time. In addition to metal plugged vias, our glass interposers are capable of fiber and antennae solutions providing two additional very high density and ultra-high speed data transfer capabilities.

36 MATERIALS SCIENCE↗
DOE OSTI2019

High Density Chip Interconnect Technology Using High Density Glass Interposers

Modern particle physics experiments require “intelligent detectors” with dense interconnects and distributed intelligence in very large area detector systems. Available packaging and interconnect technologies directly limit the performance and capabilities of these systems. Interposers are interconnected elements that use through-silicon or through-glass via to replace the PC board technology currently used for connecting chips and can improve the interconnect density by more than two orders of magnitude. The goal of this project is to fabricate a thru glass via interposer that will allow top to bottom side interconnects in the tens of microns. Having a thru glass interposer with interconnects in the tens of microns will benefit the electrons industry which focuses on 3D packaging. In addition to commercial, medical applications such as the CAT scan, which have resolutions in the micron or larger range, will now be able to use these interposers to diagnose in the tens of microns.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

Antenna With Embedded Die in Glass Interposer for 6G Wireless Applications

This article presents the antenna-integrated glass interposer for D-band 6G wireless applications using dieembedding technology. Here, we implement the die-embedded package on glass substrates and characterize the electrical performance in the D-band. The electrical characterization employs embedded test dies with the 50-Ω ground–signal–ground (GSG) ports and coplanar waveguides. We achieve low-loss die-to-package transitions by using staggered dielectric vias, which are compared with the transitions of wire-bonding and flip-chip assembly. This article provides detailed information on the design, modeling, fabrication, and characterization of the die-to-package interconnects. This article also demonstrates the integration of microstrip patch antenna array and embedded dies in the D-band. The results show superior electrical performance provided by the die-embedded glass interposer. The die-to-package interconnect exhibits good matching (less than —10-dB S11) and low loss (0.2-dB loss) in the D-band. The integrated 1 × 8 patch antenna array shows 11.6-dB broadside gain and good matching with the embedded die. In addition, by using a temporary carrier, the antenna-integrated glass interposer also has great potential for further heterogeneous integration and thermal management.

42 ENGINEERING↗
DOE OSTI2026

Impact of Interposer Microstructure on Ionic Transport in Liquid-Phase Bicarbonate Electrolysis

The electrochemical reduction of CO 2 (CO 2 RR) is a potentially scalable approach for converting captured carbon dioxide into value-added products. Conventional gas-phase electrolysis systems can suffer from carbonate crossover, which limits the efficiency of the system. Liquid-phase (bi)carbonate electrolysis using bipolar membrane electrode assemblies (BPMMEA) has emerged as a promising alternative. The interposer layer, a porous mass-transport material between the BPM and the catalyst, is an essential component of the MEA, as it allows evolved CO 2 to reach the catalyst surface for reaction. In the absence of this layer, evolved CO 2 generated by the pH swing process at the BPM can be converted back into (bi)carbonate (CO 2 recapture) due to the high bulk pH. Thus, clear design guidelines are needed to maximize CO 2 conversion, minimize CO 2 recapture in the catholyte, and improve energy efficiency. Here, the transport properties of the interposer are systematically characterized by X-ray tomography and symmetric-cell impedance spectroscopy to quantify porosity, tortuosity, and the resulting MacMullin number. We then examine the correlation between these material properties and the electrolyzer performance. We focus on characterizing two commercial porous membrane filters, mixed cellulose ester (MCE) and poly(ether sulfone) (PES).

CO2 electrolysis↗
NASA NTRS2020

An embedded planar-foil capacitor material, FPGA based interposer, aimed at improving system performance and reduced board size for space based electronics

This paper presents work to date in developing, and testing an embedded planar-foil capacitor based interposer intended to be integrated together with high-density components such as Field Programmable Gate Arrays (FPGAs), and Application Specific Integrated Circuits (ASIC). FPGA devices typically have a large number of I/O and power pins. The high speed enabled by these devices requires a large number of discrete bypass capacitors as close as possible to the power pins. These capacitors take up a considerable amount of the board area on the application circuit board. The developed interposer replaces these components freeing up space of traditional bypass capacitors for other circuitry.

Cheng, Ben↗
DOE OSTI2021

Interposed pulsed power system for fast separation of radioactive beams

This paper presents the novel design of an interposed pulsed power system, developed to drive a fast-switching magnet with a large multi-mH load inductance, and high field amplitude (> 1 T). This modulator can produce variable flat-top pulses from 1 to 30 ms with rise and fall times of less than 0.5 ms at a variable duty cycle of 3–91% into a heavily inductive load. The system employs a novel over-voltage topology to overcome the inherent inductance and achieve the fast rise and fall times, switching to a precision DC supply to efficiently maintain the flattop without requiring many-kV voltage. We present a power source design consideration, including the results of computer modeling as well as the first experimental results of a modulator scaled test model will also be presented.

47 OTHER INSTRUMENTATION↗
DOE OSTI2015

Through-silicon via-induced strain distribution in silicon interposer

Strain in silicon induced by Through-Silicon Via (TSV) integration is of particular interest in the frame of the integration of active devices in silicon interposer. Nano-focused X-ray beam diffraction experiments were conducted using synchrotron radiation to investigate the thermally induced strain field in silicon around copper filled TSVs. Measurements were performed on thinned samples at room temperature and during in situ annealing at 400 °C. In order to correlate the 2D strain maps with finite elements analysis, an analytical model was developed, which takes into account beam absorption in the sample for a given diffraction geometry. The strain field along the [335] direction is found to be in the 10{sup −5} range at room temperature and around 10{sup −4} at 400 °C. Simulations support the expected plastification in some regions of the TSV during the annealing step.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2017

Enhanced magnetoelectric coupling in a composite multiferroic system via interposing a thin film polymer

Enhancing the magnetoelectric coupling in a strain-mediated multiferroic composite structure plays a vital role in controlling magnetism by electric fields. An enhancement of magnetoelastic coupling between ferroelectric single crystal (011)-cut [Pb(Mg 1/3 Nb 2/3 )O 3 ] (1-x) -[PbTiO 3 ] x (PMN-PT, x≈ 0.30) and ferromagnetic polycrystalline Ni thin film through an interposed benzocyclobutene polymer thin film is reported. A nearly twofold increase in sensitivity of remanent magnetization in the Ni thin film to an applied electric field is observed. This observation suggests a viable method of improving the magnetoelectric response in these composite multiferroic systems.

36 MATERIALS SCIENCE↗
DOE OSTI2016

BOW posting for interposer fabrication

The Contractor shall provide the capability of fabricating Cu interposer wafers to Sandia National Laboratories (Sandia) or (SNL), located in Albuquerque, New Mexico.

42 ENGINEERING↗
DOE OSTI2021

TEMPI: An Interposed MPI Library with Canonical Representation of MPI Datatypes [Slides]

These points are covered in this presentation: Distributed GPU stencil, non-contiguous data; Equivalence of strided datatypes and minimal representation; GPU communication methods; Deploying on managed systems; Large messages and MPI datatypes; Translation and canonicalization; Automatic model-driven transfer method selection; and Interposed library implementation.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

TEMPI: An Interposed MPI Library with Canonical Representation of MPI Datatypes [Poster]

TEMPI provides a transparent non-contiguous data-handling layer compatible with various MPIs. MPI Datatypes are a powerful abstraction for allowing an MPI implementation to operate on non-contiguous data. CUDA-aware MPI implementations must also manage transfer of such data between the host system and GPU. The non-unique and recursive nature of MPI datatypes mean that providing fast GPU handling is a challenge. The same noncontiguous pattern may be described in a variety of ways, all of which should be treated equivalently by an implementation. This work introduces a novel technique to do this for strided datatypes. Methods for transferring non-contiguous data between the CPU and GPU depends on the properties of the data layout. This work shows that a simple performance model can accurately select the fastest method. Unfortunately, the combination of MPI software and system hardware available may not provide sufficient performance. The contributions of this work are deployed on OLCF Summit through an interposer library which does not require privileged access to the system to use

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Payload interposer (PIP) system and control software

A payload interposer (PIP) system and its control software provide an interface between a space vehicle and a payload. The PIP board facilitates power and communications between a command and data handler (CDH) of the space vehicle and the payload. A microcontroller of the PIP board may control operation of the payload, format messages between the space vehicle and the payload, and extract data from the payload for downlink via the space vehicle.

42 ENGINEERING↗
DOE OSTI2021

Space vehicle system and payload interposer (PIP) board

A payload interposer (PIP) board provides an interface for hosting payloads on a space vehicle platform. Payload development may be performed via the PIP board in a manner that “abstracts” the hardware of the space vehicle from the payload developer. The PIP board may include a host side payload interface connector that connects to a space vehicle and a payload side payload interface connector that connects to a payload. Power, CDH, and other space vehicle functionality may thus be provided to the payload from the space vehicle via the PIP board.

Proicou, Michael↗