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Results for “wafer bonding”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

200 mm sensor development using bonded wafers

Sensors fabricated from high resistivity, float zone, silicon material have been the basis of vertex detectors and trackers for the last 30 years. The areas of these devices have increased from a few square cm to > 200m 2 for the existing CMS tracker. High Luminosity Large Hadron Collider (HL-LHC), CMS and ATLAS tracker upgrades will each require more than 200 m 2 of silicon and the CMS High Granularity Calorimeter (HGCAL) will require more than 600 m 2 . The cost and complexity of assembly of these devices is related to the area of each module, which in turn is set by the size of the silicon sensors. In addition to large area, the devices must be radiation hard, which requires the use of sensors thinned to 200 microns or less. The combination of wafer thinning and large wafer diameter is a significant technical challenge, and is the subject of this work. In this paper we describe work on development of thin sensors on 200 mm wafers using wafer bonding technology. Results of development runs with float zone, Silicon-on-Insulator and Silicon-Silicon bonded wafer technologies are reported.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

Trap Passivation for Reducing On-Resistance and Saturation Voltage in Wafer-Bonded InGaAs-Channel/GaN-Drain Vertical FETs

High frequency and high power are the driving forces behind semiconductor transistor technology. However, conventional devices have the tradeoff of either being high speed or high breakdown—but not both. Wafer-bonded current aperture vertical electron transistors (BAVETs) help eliminate the tradeoff by combining a high-speed III-As channel to a high-breakdown III-N drift region. The device presented herein comprises of an InAlAs gate-barrier/InGaAs channel, wafer-bonded to an InGaN/GaN drift region, with the InGaAs/InGaN interface referred to as the wafer-bonded interface (WBI). The electronic behavior of WBIs is yet less known but necessary in realizing the potential of a BAVET. Herein, strong trap activity at the WBI is shown to be the cause of abnormally high saturation voltage ( V DS_SAT ) in BAVETs. The traps cause unintentional space charge (SC) region in the drain region of the device. This causes a drain resistance, a higher ON-resistance ( R ON ), and a higher V DS_SAT . Here, the challenge is overcome by hydrogen passivation of traps at WBI by using a p-doping for the InAlAs layer, which reduces the trap-charge concentration at the WBI. Consequently, the width of the SC region is reduced and a reduction in V DS_SAT is demonstrated, wherein it reduces from >12 to 5 V.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Role of humidity and surface roughness on direct wafer bonding

Bodies made from elastically stiff material usually bind very weakly unless the surfaces are flat and extremely smooth. In direct wafer bonding flat surfaces bind by capillary bridges and by the van der Waals interaction, which act between all solid objects. Here we study the dependency of the work of adhesion on the humidity and surface roughness in hydrophilic direct wafer bonding. We show that the long-wavelength roughness (usually denoted waviness) has a negligible influence on the strength of wafer bonding (the work of adhesion) from the menisci that form from capillary condensation of water vapor.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
NASA NTRS2004

A Wafer-Bonded, Floating Element Shear-Stress Sensor Using a Geometric Moire Optical Transduction Technique

This paper presents a geometric Moir optical-based floating-element shear stress sensor for wind tunnel turbulence measurements. The sensor was fabricated using an aligned wafer-bond/thin-back process producing optical gratings on the backside of a floating element and on the top surface of the support wafer. Measured results indicate a static sensitivity of 0.26 microns/Pa, a resonant frequency of 1.7 kHz, and a noise floor of 6.2 mPa/(square root)Hz.

Horowitz, Stephen↗
NASA NTRS2007

Wafer bonded virtual substrate and method for forming the same

A method of forming a virtual substrate comprised of an optoelectronic device substrate and handle substrate comprises the steps of initiating bonding of the device substrate to the handle substrate, improving or increasing the mechanical strength of the device and handle substrates, and thinning the device substrate to leave a single-crystal film on the virtual substrate such as by exfoliation of a device film from the device substrate. The handle substrate is typically Si or other inexpensive common substrate material, while the optoelectronic device substrate is formed of more expensive and specialized electro-optic material. Using the methodology of the invention a wide variety of thin film electro-optic materials of high quality can be bonded to inexpensive substrates which serve as the mechanical support for an optoelectronic device layer fabricated in the thin film electro-optic material.

Atwater, Jr., Harry A.↗
NASA NTRS2008

Wafer bonded epitaxial templates for silicon heterostructures

A heterostructure device layer is epitaxially grown on a virtual substrate, such as an InP/InGaAs/InP double heterostructure. A device substrate and a handle substrate form the virtual substrate. The device substrate is bonded to the handle substrate and is composed of a material suitable for fabrication of optoelectronic devices. The handle substrate is composed of a material suitable for providing mechanical support. The mechanical strength of the device and handle substrates is improved and the device substrate is thinned to leave a single-crystal film on the virtual substrate such as by exfoliation of a device film from the device substrate. An upper portion of the device film exfoliated from the device substrate is removed to provide a smoother and less defect prone surface for an optoelectronic device. A heterostructure is epitaxially grown on the smoothed surface in which an optoelectronic device may be fabricated.

Atwater, Harry A., Jr.↗
NASA NTRS2016

Fabricating with Crystalline Si to Improve Superconducting Detector Performance

We built and measured radio-frequency (RF) loss tangent, tan d, evaluation structures using float-zone quality silicon-on-insulator (SOI) wafers with 5 µ m thick device layers. Superconducting Nb components were fabricated on both sides of the SOI Si device layer. Our main goals were to develop a robust fabrication for using crystalline Si (c-Si) dielectric layers with superconducting Nb components in a wafer bonding process and to confirm that tan d with c-Si dielectric layers was reduced at RF frequencies compared to devices fabricated with amorphous dielectrics, such as SiO2 and SixNy, where tan d ~ 10-3. Our primary test structure used a Nb coplanar waveguide (CPW) readout structure capacitively coupled to LC resonators, where the capacitors were defined as parallel-plate capacitors on both sides of a c-Si device layer using a wafer bonding process with benzocyclobutene (BCB) wafer bonding adhesive. Our control experiment, to determine the intrinsic tan d in the SOI device layer without wafer bonding, also used Nb CPW readout coupled to LC resonators; however, the parallel-plate capacitors were fabricated on both sides of the Si device layer using a deep reactive ion etch (DRIE) to access the c-Si underside through the buried oxide and handle Si layers in the SOI wafers. We found that our wafer bonded devices demonstrated F· d = (8 ± 2) × 10-5, where F is the filling fraction of two-level states (TLS). For the control experiment, F· d = (2.0 ± 0.6) × 10-5, and we discuss what may be degrading the performance in the wafer bonded devices as compared to the control devices.

Beyer, A D↗
NASA NTRS2016

Fabricating with Crystalline Si to Improve Superconducting Detector Performance

We built and measured radio-frequency (RF) loss tangent, tan δ, evaluation structures using float-zone quality silicon-on-insulator (SOI) wafers with 5 μm thick device layers. Superconducting Nb components were fabricated on both sides of the SOI Si device layer. Our main goals were to develop a robust fabrication for using crystalline Si (c-Si) dielectric layers with superconducting Nb components in a wafer bonding process and to confirm that tan δ with c-Si dielectric layers was reduced at RF frequencies compared to devices fabricated with amorphous dielectrics, such as SiO2 and SixNy, where tan δ ~ 10(exp -3). Our primary test structure used a Nb coplanar waveguide (CPW) readout structure capacitively coupled to LC resonators, where the capacitors were defined as parallel-plate capacitors on both sides of a c-Si device layer using a wafer bonding process with benzocyclobutene (BCB) wafer bonding adhesive. Our control experiment, to determine the intrinsic tan δ in the SOI device layer without wafer bonding, also used Nb CPW readout coupled to LC resonators; however, the parallel-plate capacitors were fabricated on both sides of the Si device layer using a deep reactive ion etch (DRIE) to access the c-Si underside through the buried oxide and handle Si layers in the SOI wafers. We found that our wafer bonded devices demonstrated F· δ = (8 +/- 2) × 10(exp -5), where F is the filling fraction of two-level states (TLS). For the control experiment, F· δ = (2.0 +/- 0.6) × 10(exp -5), and we discuss what may be degrading the performance in the wafer bonded devices as compared to the control devices.

Beyer, A. D↗
NASA NTRS2009

Fabrication of an Antenna-Coupled Bolometer for Cosmic Microwave Background Polarimetry

We describe the development of a detector for precise measurements of the cosmic microwave background polarization. The detector employs a waveguide to couple light between a pair of Mo/Au superconducting transition edge sensors (TES) and a feedhorn. Incorporation of an on-chip ortho-mode transducer (OMT) results in high isolation. The OMT is micromachined and bonded to the microstrip and TES circuits in a low temperature wafer bonding process. The wafer bonding process incorporates a buried superconducting niobium layer with a single crystal silicon layer which serves as the leg isolated TES membrane and as the microstrip dielectric. We describe the micromachining and wafer bonding process and report measurement results of the microwave circuitry operating in the 29-43GHz band along with Johnson noise measurements of the TES membrane structures and development of Mo/Au TES operating under '00mK.

Denis, K.L.↗
NASA NTRS2007

Multiple internal seal right micro-electro-mechanical system vacuum package

A Multiple Internal Seal Ring (MISR) Micro-Electro-Mechanical System (MEMS) vacuum package that hermetically seals MEMS devices using MISR. The method bonds a capping plate having metal seal rings to a base plate having metal seal rings by wafer bonding the capping plate wafer to the base plate wafer. Bulk electrodes may be used to provide conductive paths between the seal rings on the base plate and the capping plate. All seals are made using only metal-to-metal seal rings deposited on the polished surfaces of the base plate and capping plate wafers. However, multiple electrical feed-through metal traces are provided by fabricating via holes through the capping plate for electrical connection from the outside of the package through the via-holes to the inside of the package. Each metal seal ring serves the dual purposes of hermetic sealing and providing the electrical feed-through metal trace.

Hayworth, Ken J.↗
NASA NTRS2008

Multiple internal seal ring micro-electro-mechanical system vacuum packaging method

A Multiple Internal Seal Ring (MISR) Micro-Electro-Mechanical System (MEMS) vacuum packaging method that hermetically seals MEMS devices using MISR. The method bonds a capping plate having metal seal rings to a base plate having metal seal rings by wafer bonding the capping plate wafer to the base plate wafer. Bulk electrodes may be used to provide conductive paths between the seal rings on the base plate and the capping plate. All seals are made using only metal-to-metal seal rings deposited on the polished surfaces of the base plate and capping plate wafers. However, multiple electrical feed-through metal traces are provided by fabricating via holes through the capping plate for electrical connection from the outside of the package through the via-holes to the inside of the package. Each metal seal ring serves the dual purposes of hermetic sealing and providing the electrical feed-through metal trace.

Hayworth, Ken J.↗
NASA NTRS2004

A Micromachined Geometric Moire Interferometric Floating-Element Shear Stress Sensor

This paper presents the development of a floating-element shear stress sensor that permits the direct measurement of skin friction based on geometric Moir interferometry. The sensor was fabricated using an aligned wafer-bond/thin-back process producing optical gratings on the backside of a floating element and on the top surface of the support wafer. Experimental characterization indicates a static sensitivity of 0.26 microns/Pa, a resonant frequency of 1.7 kHz, and a noise floor of 6.2 mPa/(square root)Hz.

Horowitz, S.↗
NASA NTRS1995

Integrated Microreactor for Chemical and Biochemical Applications

A completely integrated microreactor was developed that allows for the processing of very small amounts of chemical solutions. The entire system comprises several pumps and valves arranged in different branches as well as a mixing unit and a reaction chamber. The streaming path of each branch contains two valves and one pump each. The pumps are driven by piezoelectric elements mounted on thin glass membranes. Each pump is about 3.5 mm x 3.5 mm x 0.7 mm. A pumping rate up to 25 microliters per hour can be achieved. The operational voltage ranges between 40 and 200 V. A volume stroke up to 1.5 millimeter is achievable from the membrane structures. The valves are designed as passive valves. Sealing is by thin metal films. The dimension of a valve unit is 0.8 x 0.8. 07 mm. The ends of the separate streaming branches are arranged to meet in one point. This point acts as the beginning of a mixer unit which contains several fork-shaped channels. The arrangement of these channels allows for the division of the whole liquid stream into partial streams and their reuniting. A homogeneous mixing of solutions and/or gases can be observed after having passed about 10 of the fork elements. A reaction chamber is arranged behind the mixing unit to support the chemical reaction of special fluids. This unit contains heating elements placed outside of the chamber. The complete system is arranged in a modular structure and is built up of silicon. It comprises three silicon wafers bonded together by applying the silicon direct bonding technology. The silicon structures are made only by wet chemical etching processes. The fluid connections to the outside are realized using standard injection needles glued into v-shaped structures on the silicon wafers. It is possible to integrate other components, like sensors or electronic circuits using silicon as the basic material.

Schwesinger, N.↗