Engineering topics

Buehler, Martin G.

Publications and source records attributed to Buehler, Martin G..

At least 37 records · Page 2

NASA NTRS1991

Addressable-Matrix Integrated-Circuit Test Structure

Method of quality control based on use of row- and column-addressable test structure speeds collection of data on widths of resistor lines and coverage of steps in integrated circuits. By use of straightforward mathematical model, line widths and step coverages deduced from measurements of electrical resistances in each of various combinations of lines, steps, and bridges addressable in test structure. Intended for use in evaluating processes and equipment used in manufacture of application-specific integrated circuits.

Sayah, Hoshyar R.↗

NASA NTRS1991

Asymmetric soft-error resistant memory

A memory system is provided, of the type that includes an error-correcting circuit that detects and corrects, that more efficiently utilizes the capacity of a memory formed of groups of binary cells whose states can be inadvertently switched by ionizing radiation. Each memory cell has an asymmetric geometry, so that ionizing radiation causes a significantly greater probability of errors in one state than in the opposite state (e.g., an erroneous switch from '1' to '0' is far more likely than a switch from '0' to'1'. An asymmetric error correcting coding circuit can be used with the asymmetric memory cells, which requires fewer bits than an efficient symmetric error correcting code.

Buehler, Martin G.↗

NASA NTRS1991

Five-Segment Interconnection For Electromigration Tests

Proposed integrated-circuit conductive pattern intended for use in electromigration lifetime testing of interconnection lines of integrated circuits. Designed for collection of statistics on electromigration from smallest possible area. Includes 5 interconnection segments with Kelvin voltage taps, with total of 12 contact pads, and provides for simultaneous measurements on all of segments. Attempts to minimize thermal gradients within each segment and conforms to guidelines on electromigration test structures promulgated by National Institute of Standards and Technology (NIST).

Hannaman, David J.↗

NASA NTRS1991

Designing Accelerated Tests Of Electromigration

Method for design of accelerated tests of electromigration (as in microscopic conductors in integrated circuits) based partly on simplified mathematical model of electromigration and partly on error analysis. Objective to determine quickly operating life of tested components under normal operating conditions by extrapolation from lifetime measurements at operating stresses greater than normal. Involves compromise between reducing testing time by increasing stresses and reducing uncertainty in extrapolated lifetime by decreasing stresses.

Buehler, Martin G.↗

NASA NTRS1991

Cross-Quint-Bridge Resistor

Integrated-circuit conductive test pattern intended to provide data on effects of design widths and design spacings upon actual widths of conductive lines. Provides for electrical measurements both on lines of unknown width and on features having known dimensions. Data from measurements on five bridges used to determine four parameters of mathematical model describing system. In principle, pattern determines effects of width and spacing and interaction between them.

Hannaman, David J.↗

NASA NTRS1990

Integrated circuit reliability testing

A technique is described for use in determining the reliability of microscopic conductors deposited on an uneven surface of an integrated circuit device. A wafer containing integrated circuit chips is formed with a test area having regions of different heights. At the time the conductors are formed on the chip areas of the wafer, an elongated serpentine assay conductor is deposited on the test area so the assay conductor extends over multiple steps between regions of different heights. Also, a first test conductor is deposited in the test area upon a uniform region of first height, and a second test conductor is deposited in the test area upon a uniform region of second height. The occurrence of high resistances at the steps between regions of different height is indicated by deriving the measured length of the serpentine conductor using the resistance measured between the ends of the serpentine conductor, and comparing that to the design length of the serpentine conductor. The percentage by which the measured length exceeds the design length, at which the integrated circuit will be discarded, depends on the required reliability of the integrated circuit.

Buehler, Martin G.↗

NASA NTRS1990

Exact Chord-Length Distribution For SEU Calculations

Computed rates of SEU's more accurate. Exact integral chord-length distribution derived for use in calculations of rates of single-event upsets (SEU's) (changes in logic states) caused by impingement of cosmic rays or other ionizing radiation on electronic logic circuits.

Buehler, Martin G.↗

NASA NTRS1990

Thermal-Interaction Matrix For Resistive Test Structure

Linear mathematical model predicts increase in temperature in each segment of 15-segment resistive structure used to test electromigration. Assumption of linearity based on fact: equations that govern flow of heat are linear and coefficients in equations (heat conductivities and capacities) depend only weakly on temperature and considered constant over limited range of temperature.

Buehler, Martin G.↗

NASA NTRS1990

Asymmetric Memory Circuit Would Resist Soft Errors

Some nonlinear error-correcting codes more efficient in presence of asymmetry. Combination of circuit-design and coding concepts expected to make integrated-circuit random-access memories more resistant to "soft" errors (temporary bit errors, also called "single-event upsets" due to ionizing radiation). Integrated circuit of new type made deliberately more susceptible to one kind of bit error than to other, and associated error-correcting code adapted to exploit this asymmetry in error probabilities.

Buehler, Martin G.↗

NASA NTRS1989

Test Structures For Bumpy Integrated Circuits

Cross-bridge resistors added to comb and serpentine patterns. Improved combination of test structures built into integrated circuit used to evaluate design rules, fabrication processes, and quality of interconnections. Consist of meshing serpentines and combs, and cross bridge. Structures used to make electrical measurements revealing defects in design or fabrication. Combination of test structures includes three comb arrays, two serpentine arrays, and cross bridge. Made of aluminum or polycrystalline silicon, depending on material in integrated-circuit layers evaluated. Aluminum combs and serpentine arrays deposited over steps made by polycrystalline silicon and diffusion layers, while polycrystalline silicon versions of these structures used to cross over steps made by thick oxide layer.

Buehler, Martin G.↗

NASA NTRS1989

Asymmetrical SRAM Cells For Radiation Tests

Features of circuits altered to increase or decrease sensitivity to radiation. State-space analysis used to analyze single-event-upset behavior of memory cell. When voltage on node a is set at one of indicated initial values Vao and then released, voltages on nodes a and b then follow indicated trajectory to final logic "one" or logic "zero" state. Ability to do this important for design of radiation-detecting integrated circuits (deliberately made more sensitive to ionizing radiation) and "radiation-hardened" integrated circuits - those intended to be relatively invulnerable to intense radiation.

Buehler, Martin G.↗

NASA NTRS1989

Timing Sampler For Delay Measurements

Integrated circuit called timing sampler used to measure delays in complementary metal oxide/silicon logic gates. Circuit chip contains chains of inverters and metal traces having minimum parasitic delays (delay chains), circuits to compare pulse timings, and output multiplexer. Timing sampler enables delay measurements for both positive and negative logic-level transitions by use of variety of circuit geometries representing tentative practical designs.

Blaes, Brent R.↗

NASA NTRS1988

Integrated circuit reliability testing

Buehler, Martin G.↗

NASA NTRS1988

An exact, closed-form expression of the integral chord-length distribution for the calculation of single-event upsets induced by cosmic rays

This paper presents a derivation of an exact closed-form expression of the integral chord-length distribution for the calculation of single-event upsets (SEUs) in an electronic memory cell, caused by cosmic rays. Results computed for two rectangular parallelepipeds using this exact expression are compared with those computed with Bradford's (1979) semiexact expression of C(x). It is found that the values of C(x) are identical for x equal or smaller than b but are vastly different for x greater than b. Moreover, while C(x) of Bradford gives reasonably accurate values of SEU rate for certain sets of computational parameters, it gives values more than 10 times larger than the correct values for other sets of parameters.

Luke, Keung L.↗

NASA NTRS1988

Measuring Critical Charges For Single-Event Upsets

Concept for determining susceptibility of integrated circuits to single-event upsets (SEU's) based on direct measurement of critical charge causing upset. Test circuit is modified version of standard complementary metal-oxide/semiconductor static cell. Contains six transistors, connected to form latch that retains state of cell set by input pulses. Makes possible to evaluate vulnerability to SEU during design and development of digital equipment.

Buehler, Martin G.↗

NASA NTRS1988

Addressable Inverter Matrix Tests Integrated-Circuit Wafer

Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

Buehler, Martin G.↗

NASA NTRS1988

Comb/serpentine/cross-bridge test structure for fabrication process evaluation

The comb/serpentine/cross-bridge structure was developed to monitor and evaluate same layer shorts and step coverage problems (open and high-resistance wire over steps) for integrated circuit fabrication processes. The cross-bridge provides local measurements of wire sheet resistance and wirewidth. These local parametric measurements are used in the analysis of the serpentine wire, which identifies step coverage problems. The comb/serpentine/cross-bridge structure was fabricated with 3 microns CMOS/bulk p-well process and tested using a computer-controlled parametric test system.

Sayah, Hoshyar R.↗

NASA NTRS1988

Addressable test matrix for measuring analog transfer characteristics of test elements used for integrated process control and device evaluation

A set of addressable test structures, each of which uses addressing schemes to access individual elements of the structure in a matrix, is used to test the quality of a wafer before integrated circuits produced thereon are diced, packaged and subjected to final testing. The electrical characteristic of each element is checked and compared to the electrical characteristic of all other like elements in the matrix. The effectiveness of the addressable test matrix is in readily analyzing the electrical characteristics of the test elements and in providing diagnostic information.

Buehler, Martin G.↗