Engineering topics
Publications and source records attributed to Ramondetta, P..
Report describes processes used in making complementary - metal - oxide - semiconductor/silicon-on-sapphire (CMOS/SOS) integrated circuits. Report lists processing steps ranging from initial preparation of sapphire wafers to final mapping of "good" and "bad" circuits on a wafer.
Report documents life cycles of two custom CMOS integrated circuits: (1) 4-bit multiplexed register with shift left and shift right capabilities, and (2) dual 4-bit registers. Cycles described include conception as logic diagrams through design, fabrication, testing, and delivery.
Major silicon-gate CMOS/SOS processes are described. Sapphire substrate preparation is also discussed, as well as the following process variations: (1) the double epi process; and (2) ion implantation.
A description of the MOS transistor used in the FETSIM analysis program is presented. CMOS/SOS device parameters are included. Typical device mobilities are given as well as the empirically determined constants necessary to model second-order effect conductance variations due to gate voltage and saturated drain voltage.
The important features of the multiport (double entry) automatic placement and routing programs for standard cells are described. Measured performance and predicted performance were compared for seven CMOS/SOS array types and hybrids designed with the high speed CMOS/SOS cell family. The CMOS/SOS standard cell data sheets are listed and described.
Automatic design technique uses standard circuit cells for producing large-scale integrated arrays. Computerized fabrication process provides individual cells of high density and efficiency, quick turnaround time, low cost, and ease of corrections for changes and errors.
A low cost, quick turnaround technique for generating custom metal oxide semiconductor arrays using the standard cell approach was developed, implemented, tested and validated. Basic cell design topology and guidelines are defined based on an extensive analysis that includes circuit, layout, process, array topology and required performance considerations particularly high circuit speed.